Datasheet

PCF2127AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 July 2013 38 of 86
NXP Semiconductors
PCF2127AT
Integrated RTC, TCXO and quartz crystal
8.11.2 Register Watchdg_tim_val
8.11.3 Watchdog timer function
The watchdog timer function is enabled or disabled by the WD_CD[1:0] bits of the register
Watchdg_tim_ctl (see Table 35
).
The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock
frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or
1
⁄
60
Hz (see Table 37).
When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val
determines the watchdog timer period (see Table 36
).
The watchdog timer counts down from the software programmed 8-bit binary value n in
register Watchdg_tim_val. When the counter reaches 1, the watchdog timer flag WDTF
(register Control_2) is set logic 1.
If WDTF is logic 1 and:
• if WD_CD[1:0] = 10 an interrupt will be generated
• if WD_CD[1:0] = 11 a reset will be generated
The counter does not automatically reload.
When WD_CD[1:0] = 10 or WD_CD[1:0] = 11 and the microcontroller unit (MCU) loads a
watchdog timer value n:
• the flag WDTF is reset
• INT or RST is cleared
• the watchdog timer starts again
Loading the counter with 0 will:
• reset the flag WDTF
• clear INT or RST
• stop the watchdog timer
Table 36. Watchdg_tim_val - watchdog timer value register (address 11h) bit description
Bit Symbol Value Description
7 to 0 WATCHDG_TIM_VAL[7:0] 00 to FF timer period in seconds:
where n is the timer value
Table 37. Programmable watchdog or countdown timer
TF[1:0] Timer source
clock frequency
Units Minimum timer
period (n = 1)
Units Maximum timer
period (n = 255)
Units
00 4.096 kHz 244 s 62.256 ms
01 64 Hz 15.625 ms 3.984 s
10 1 Hz 1 s 255 s
11
1
⁄
60
Hz 60 s 15300 s
CountdownPeriod
n
SourceClockFrequency
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