Datasheet

PCF2127AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 July 2013 41 of 86
NXP Semiconductors
PCF2127AT
Integrated RTC, TCXO and quartz crystal
If this mode is enabled and the countdown timer flag CDTF is set, an interrupt signal on
INT
will be generated. See Section 8.13.2 for details on how the interrupt can be
controlled.
When starting the countdown timer for the first time, only the first period will not have a
fixed duration. The amount of inaccuracy for the first timer period will depend on the
chosen source clock, see Table 39
.
At the end of every countdown, the timer sets the countdown timer flag (CDTF). CDTF
may only be cleared by command. The asserted CDTF can be used to generate an
interrupt (INT
). The interrupt may be generated as a pulsed signal every countdown
period or as a permanently active signal which follows the condition of CDTF. TI_TP is
used to control this mode selection. The interrupt output may be disabled with the CDTIE
bit, see Table 7
.
When reading the timer, the actual countdown value is returned and not the initial value n.
Since it is not possible to freeze the countdown timer counter during read back, it is
recommended to read the register twice and check for consistent results.
8.11.5 Pre-defined timers: second and minute interrupt
PCF2127AT has two pre-defined timers which are used to generate an interrupt either
once per second or once per minute. The pulse generator for the minute or second
interrupt operates from an internal 64 Hz clock. It is independent of the watchdog or
countdown timers. Each of these timers can be enabled by the bits SI (second interrupt)
and MI (minute interrupt) in register Control_1.
8.11.6 Clearing flags
The flags MSF, CDTF, AF and TSFx can be cleared by command. To prevent one flag
being overwritten while clearing another, a logic AND is performed during the write
access. A flag is cleared by writing logic 0 while a flag is not cleared by writing logic1.
Writing logic1 will result in the flag value remaining unchanged.
Four examples are given for clearing the flags. Clearing the flags is made by a write
command:
• Bits labeled with - must be written with their previous values
• WDTF is read only and has to be written with logic 0
Repeatedly rewriting these bits has no influence on the functional behavior.
Table 39. First period delay for timer counter
Timer source clock Minimum timer period Maximum timer period
4.096 kHz n n + 1
64 Hz n n + 1
1 Hz (n  1) +
1
⁄
64
Hz n +
1
⁄
64
Hz
1
⁄
60
Hz (n  1) +
1
⁄
64
Hz n +
1
⁄
64
Hz
Table 40. Flag location in register Control_2
Register Bit
7 6 5 4 3 2 1 0
Control_2 MSF WDTF TSF2 AF CDTF - - -