Datasheet

PCF2127AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 July 2013 50 of 86
NXP Semiconductors
PCF2127AT
Integrated RTC, TCXO and quartz crystal
8.13.3 INT pulse shortening
The pulse generator for the countdown timer interrupt also uses an internal clock, but this
time it is dependent on the selected source clock for the countdown timer and on the
countdown value n. As a consequence, the width of the interrupt pulse varies (see
Table 55
).
[1] n = loaded countdown value. Timer stopped when n = 0.
If the MSF or CDTF flag (register Control_2) is cleared before the end of the INT pulse,
then the INT
pulse is shortened. This allows the source of a system interrupt to be cleared
immediately when it is serviced, that is, the system does not have to wait for the
completion of the pulse before continuing, see Figure 28
and Figure 29. Instructions for
clearing bit MSF and bit CDTF can be found in Section 8.11.6
.
Table 55. INT operation (bit TI_TP = 1)
Source clock (Hz) INT period (s)
n = 1
[1]
n > 1
4096
1
⁄
8192
1
⁄
4096
64
1
⁄
128
1
⁄
64
1
1
⁄
64
1
⁄
64
1
⁄
60
1
⁄
64
1
⁄
64
(1) Indicates normal duration of INT pulse.
The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode,
that is,
when TI_TP is logic 0, where the INT
pulse may be shortened by setting both bits MI and SI
logic 0.
Fig 28. Example of shortening the INT pulse by clearing the MSF flag
001aaf908
58seconds counter
MSF
INT
SCL
instruction
59
CLEAR INSTRUCTION
8th clock
(1)