Datasheet

PCF2127AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 July 2013 57 of 86
NXP Semiconductors
PCF2127AT
Integrated RTC, TCXO and quartz crystal
9.1 SPI-bus interface
Data transfer to and from the device is made by a 3 line SPI-bus (see Table 58). The data
lines for input and output are split. The data input and output line can be connected
together to facilitate a bidirectional data bus (see Figure 34
). The SPI-bus is initialized
whenever the chip enable line pin SDA/CE
is inactive.
[1] The chip enable must not be wired permanently LOW.
9.1.1 Data transmission
The chip enable signal is used to identify the transmitted data. Each data transfer is a
whole byte, with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal SDA/CE
. The first
byte transmitted is the command byte. Subsequent bytes will be either data to be written
or data to be read (see Figure 35
).
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The R/W
bit defines if the following
bytes will be read or write information.
Fig 34. SDI, SDO configurations
Table 58. Serial interface
Symbol Function Description
SDA/CE
chip enable input;
active LOW
[1]
when HIGH, the interface is reset;
input may be higher than V
DD
SCL serial clock input when SDA/CE is HIGH, input may float;
input may be higher than V
DD
SDI serial data input when SDA/CE is HIGH, input may float;
input may be higher than V
DD
;
input data is sampled on the rising edge of SCL
SDO serial data output push-pull output;
drives from V
SS
to V
BBS
;
output data is changed on the falling edge of SCL
001aai560
SDI
two wire mode
SDO
SDI
single wire mode
SDO
Fig 35. Data transfer overview
013aaa311
data bus
SDA/CE
COMMAND DATA
DATA
DATA