Datasheet

PCF2127AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 July 2013 60 of 86
NXP Semiconductors
PCF2127AT
Integrated RTC, TCXO and quartz crystal
9.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I
2
C-bus is illustrated in Figure 41.
Fig 40. System configuration
mba605
MASTER
TRANSMITTER
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER
RECEIVER
SDA
SCL
Fig 41. Acknowledgement on the I
2
C-bus
mbc602
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master