Datasheet

PCF2127AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 July 2013 61 of 86
NXP Semiconductors
PCF2127AT
Integrated RTC, TCXO and quartz crystal
9.2.5 I
2
C-bus protocol
After a start condition, a valid hardware address has to be sent to a PCF2127AT device.
The appropriate I
2
C-bus slave address is 1010001. The entire I
2
C-bus slave address byte
is shown in Table 60
.
The R/W bit defines the direction of the following single or multiple byte data transfer (read
is logic 1, write is logic 0).
For the format and the timing of the START condition (S), the STOP condition (P), and the
acknowledge bit (A) refer to the I
2
C-bus specification Ref. 11 “UM10204” and the
characteristics table (Table 65
). In the write mode, a data transfer is terminated by sending
either a STOP condition or the START condition of the next data transfer.
Table 60. I
2
C slave address byte
Slave address
Bit 7 6 5 4 3 2 1 0
MSB LSB
1010001R/W
Fig 42. Bus protocol, writing to registers
001aaj719
S 1 0 1
slave address
register address
00h to 1Dh
0 to n
data bytes
write bit
START/
STOP
acknowledge
from PCF2127AT
acknowledge
from PCF2127AT
acknowledge
from PCF2127AT
0 0 0 1 0 A A A P/S
Fig 43. Bus protocol, reading from registers
001aaj721
S 1 0 1
slave address
0 to n data bytes
DATA BYTE LAST DATA BYTE
read bit
acknowledge
from PCF2127AT
acknowledge
from master
no acknowledge
0 0 0 1 1 A A
S 1 0 1
slave address
register address
00h to 1Dh
set register
address
read register
data
write bit
STOP
acknowledge
from PCF2127AT
acknowledge
from PCF2127AT
0 0 0 1 0 A A
P
A P