Datasheet
PCF2127AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 July 2013 71 of 86
NXP Semiconductors
PCF2127AT
Integrated RTC, TCXO and quartz crystal
14. Dynamic characteristics
14.1 SPI-bus timing characteristics
[1] No load value; bus will be held up by bus capacitance; use RC time constant with application values.
Table 64. SPI-bus characteristics
V
DD
= 1.8 V to 4.2 V; V
SS
=0V; T
amb
= 40 C to +85 C, unless otherwise specified. All timing values are valid within the
operating supply voltage at ambient temperature and referenced to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
Symbol Parameter Conditions V
DD
=1.8V V
DD
=4.2V Unit
Min Max Min Max
Pin SCL
f
clk(SCL)
SCL clock frequency register read/write access - 2.0 - 6.5 MHz
RAM write access - 2.0 - 6.5 MHz
RAM read access - 1.11 - 6.25 MHz
t
SCL
SCL time register read/write access 800 - 140 - ns
RAM write access 800 - 140 - ns
RAM read access 900 - 160 - ns
t
clk(H)
clock HIGH time register read/write access 100 - 70 - ns
RAM write access 100 - 70 - ns
RAM read access 450 - 80 - ns
t
clk(L)
clock LOW time register read/write access 400 - 70 - ns
RAM write access 400 - 70 - ns
RAM read access 450 - 80 - ns
t
r
rise time for SCL signal - 100 - 100 ns
t
f
fall time for SCL signal - 100 - 100 ns
Pin SDA/CE
t
su(CE_N)
CE_N set-up time 60 - 30 - ns
t
h(CE_N)
CE_N hold time 40 - 25 - ns
t
rec(CE_N)
CE_N recovery time 100 - 30 - ns
t
w(CE_N)
CE_N pulse width - 0.99 - 0.99 s
Pin SDI
t
su
set-up time set-up time for SDI data 70 - 20 - ns
t
h
hold time hold time for SDI data 70 - 20 - ns
Pin SDO
t
d(R)SDO
SDO read delay time C
L
= 50 pF
register read access - 225 - 55 ns
RAM read access - 410 - 55 ns
t
dis(SDO)
SDO disable time
[1]
- 90 - 25 ns
t
t(SDI-SDO)
transition time from SDI to
SDO
to avoid bus conflict 0 - 0 - ns