Datasheet
PCF2127AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 July 2013 73 of 86
NXP Semiconductors
PCF2127AT
Integrated RTC, TCXO and quartz crystal
14.2 I
2
C interface timing characteristics
[1] The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus
interface if either the SDA or SCL is held LOW for a minimum of 25 ms. The bus time-out feature must be
disabled for DC operation.
[2] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of
the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
[3] C
b
is the total capacitance of one bus line in pF.
[4] The maximum t
f
for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage,
t
f
is 250 ns. This allows series protection resistors to be connected between the SDA/CE pin, the SCL pin,
and the SDA/SCL bus lines without exceeding the maximum t
f
.
[5] t
VD;ACK
is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.
[6] t
VD;DAT
is the minimum time for valid SDA (out) data following SCL LOW.
[7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
Table 65. I
2
C-bus characteristics
All timing characteristics are valid within the operating supply voltage and ambient temperature
range and reference to 30 % and 70 % with an input voltage swing of V
SS
to V
DD
(see Figure 52).
Symbol Parameter Standard mode Fast-mode (Fm) Unit
Min Max Min Max
Pin SCL
f
SCL
SCL clock frequency
[1]
0 100 0 400 kHz
t
LOW
LOW period of the SCL
clock
4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL
clock
4.0 - 0.6 - s
Pin SDA/CE
t
SU;DAT
data set-up time 250 - 100 - ns
t
HD;DAT
data hold time 0 - 0 - ns
Pins SCL and SDA/CE
t
BUF
bus free time between a
STOP and START
condition
4.7 - 1.3 - s
t
SU;STO
set-up time for STOP
condition
4.0 - 0.6 - s
t
HD;STA
hold time (repeated)
START condition
4.0 - 0.6 - s
t
SU;STA
set-up time for a
repeated START
condition
4.7 - 0.6 - s
t
r
rise time of both SDA
and SCL signals
[2][3][4]
- 1000 20 + 0.1C
b
300 ns
t
f
fall time of both SDA and
SCL signals
[2][3][4]
- 300 20 + 0.1C
b
300 ns
t
VD;ACK
data valid acknowledge
time
[5]
0.1 3.45 0.1 0.9 s
t
VD;DAT
data valid time
[6]
300 - 75 - ns
t
SP
pulse width of spikes
that must be suppressed
by the input filter
[7]
- 50 - 50 ns