Datasheet

PCF2127AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 July 2013 84 of 86
NXP Semiconductors
PCF2127AT
Integrated RTC, TCXO and quartz crystal
26. Figures
Fig 1. Block diagram of PCF2127AT . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration for SO20 (PCF2127AT) . . . . . . .4
Fig 3. Handling address registers . . . . . . . . . . . . . . . . . .6
Fig 4. Battery switch-over behavior in standard mode
with bit BIE set logic 1 (enabled) . . . . . . . . . . . . .20
Fig 5. Battery switch-over behavior in direct switching
mode with bit BIE set logic 1 (enabled) . . . . . . . .21
Fig 6. Battery switch-over circuit, simplified block
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Fig 7. Typical driving capability of V
BBS
: (V
BBS
- V
DD
)
with respect to the output load current I
BBS
. . . . .23
Fig 8. Battery low detection behavior with bit BLIE set
logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 9. Typical application of the extra power fail
detection function. . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 10. PFO
signal behavior when battery switch-over
is enabled in standard mode and
V
th(uvp)
>(V
BAT
,V
th(sw)bat
). . . . . . . . . . . . . . . . . . .25
Fig 11. PFO
signal behavior when battery switch-over is
enabled in direct switching mode and
V
th(uvp)
< V
BAT
. . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 12. PFO
signal behavior when battery switch-over is
disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 13. Power failure event due to battery discharge:
reset occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Fig 14. Dependency between POR and oscillator . . . . . .28
Fig 15. Power-On Reset (POR) system. . . . . . . . . . . . . .29
Fig 16. Power-On Reset Override (PORO) sequence,
valid for both I
2
C-bus and SPI-bus . . . . . . . . . . .29
Fig 17. Data flow of the time function. . . . . . . . . . . . . . . .33
Fig 18. Access time for read/write operations . . . . . . . . .33
Fig 19. Alarm function block diagram. . . . . . . . . . . . . . . .34
Fig 20. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .36
Fig 21. WD_CD[1:0] = 10: watchdog activates an
interrupt when timed out . . . . . . . . . . . . . . . . . . .39
Fig 22. WD_CD[1:0] = 11: watchdog activates a reset
pulse when timed out. . . . . . . . . . . . . . . . . . . . . .39
Fig 23. General countdown timer behavior . . . . . . . . . . .40
Fig 24. Timestamp detection with two push-buttons
on the TS
pin (for example, for tamper detection)43
Fig 25. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .47
Fig 26. INT
example for SI and MI when TI_TP is
logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Fig 27. INT example for SI and MI when TI_TP is
logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Fig 28. Example of shortening the INT
pulse by
clearing the MSF flag. . . . . . . . . . . . . . . . . . . . . .50
Fig 29. Example of shortening the INT
pulse by
clearing the CDTF flag. . . . . . . . . . . . . . . . . . . . .51
Fig 30. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .51
Fig 31. STOP bit functional diagram . . . . . . . . . . . . . . . .55
Fig 32. STOP bit release timing. . . . . . . . . . . . . . . . . . . .55
Fig 33. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .56
Fig 34. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .57
Fig 35. Data transfer overview. . . . . . . . . . . . . . . . . . . . .57
Fig 36. SPI-bus write example. . . . . . . . . . . . . . . . . . . . .58
Fig 37. SPI-bus read example. . . . . . . . . . . . . . . . . . . . . 58
Fig 38. Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Fig 39. Definition of START and STOP conditions . . . . . 59
Fig 40. System configuration. . . . . . . . . . . . . . . . . . . . . . 60
Fig 41. Acknowledgement on the I
2
C-bus. . . . . . . . . . . . 60
Fig 42. Bus protocol, writing to registers. . . . . . . . . . . . . 61
Fig 43. Bus protocol, reading from registers . . . . . . . . . . 61
Fig 44. Bus protocol, writing to RAM. . . . . . . . . . . . . . . . 62
Fig 45. Bus protocol, reading from RAM . . . . . . . . . . . . . 63
Fig 46. Device diode protection diagram of PCF2127AT 64
Fig 47. I
OL
on pin SDA/CE . . . . . . . . . . . . . . . . . . . . . . . 68
Fig 48. I
DD
as a function of temperature . . . . . . . . . . . . . 68
Fig 49. I
DD
as a function of V
DD
. . . . . . . . . . . . . . . . . . . . 69
Fig 50. Typical characteristic of frequency with respect
to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Fig 51. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Fig 52. I
2
C-bus timing diagram; rise and fall times refer
to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . . 74
Fig 53. Package outline SOT163-1 (SO20) . . . . . . . . . . 75
Fig 54. Tape and reel details for PCF2127AT . . . . . . . . . 76
Fig 55. Footprint information for reflow soldering of
SO20 package . . . . . . . . . . . . . . . . . . . . . . . . . . 77