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Product data sheet Rev. 7 — 19 December 2014 10 of 86

NXP Semiconductors

PCF2129

Accurate RTC with integrated quartz crystal for industrial applications

8.2 Control registers

The first 3 registers of the PCF2129, with the addresses 00h, 01h, and 02h, are used as

control registers.

8.2.1 Register Control_1

Table 6. Control_1 - control and status register 1 (address 00h) bit allocation

Bits labeled as T must always be written with logic 0.

Bit 7 6 5 4 3 2 1 0

Symbol EXT_

TEST

TSTOPTSF1POR_

OVRD

12_24 MI SI

Reset

value

00001000

Table 7. Control_1 - control and status register 1 (address 00h) bit description

Bits labeled as T must always be written with logic 0.

Bit Symbol Value Description Reference

7 EXT_TEST 0 normal mode Section 8.13

1 external clock test mode

6 T 0 unused -

5 STOP 0 RTC source clock runs Section 8.14

1 RTC clock is stopped;

RTC divider chain flip-flops are asynchronously

set logic 0;

CLKOUT at 32.768 kHz, 16.384 kHz, or

8.192 kHz is still available

4 TSF1 0 no timestamp interrupt generated Section 8.11.1

1 flag set when TS input is driven to an intermediate

level between power supply and ground;

flag must be cleared to clear interrupt

3 POR_OVRD 0 Power-On Reset Override (PORO) facility disabled;

set logic 0 for normal operation

Section 8.7.2

1 Power-On Reset Override (PORO) sequence

reception enabled

2 12_24 0 24-hour mode selected Table 27

Table 43

Table 64

1 12-hour mode selected

1 MI 0 minute interrupt disabled Section 8.12.1

1 minute interrupt enabled

0 SI 0 second interrupt disabled

1 second interrupt enabled