Datasheet
PCF2129 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 19 December 2014 25 of 86
NXP Semiconductors
PCF2129
Accurate RTC with integrated quartz crystal for industrial applications
Once the override mode is entered, the device is immediately released from the reset
state and the set-up operation can commence.
The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be
logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0
during normal operation has no effect except to prevent accidental entry into the PORO
mode.
8.8 Time and date function
Most of these registers are coded in the Binary Coded Decimal (BCD) format.
8.8.1 Register Seconds
Fig 14. Power-On Reset Override (PORO) sequence, valid for both I
2
C-bus and SPI-bus
DDM
PLQLPXPQVPLQLPXPQVPV
SRZHUXS
6&/
UHVHWRYHUULGH
6'$&(
Table 21. Seconds - seconds and clock integrity register (address 03h) bit allocation
Bits labeled as X are undefined at power-on and unchanged by subsequent resets.
Bit 7 6 5 4 3 2 1 0
Symbol OSF SECONDS (0 to 59)
Reset
value
1XXXXXXX
Table 22. Seconds - seconds and clock integrity register (address 03h) bit description
Bits labeled as X are undefined at power-on and unchanged by subsequent resets.
Bit Symbol Value Place value Description
7 OSF 0 - clock integrity is guaranteed
1 - clock integrity is not guaranteed:
oscillator has stopped and chip reset has occurred
since flag was last cleared
6 to 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format
3to0 0to9 unit place