Datasheet

Product data sheet Rev. 7 — 19 December 2014 35 of 86

NXP Semiconductors

PCF2129

Accurate RTC with integrated quartz crystal for industrial applications

8.9.5 Register Weekday_alarm

8.9.6 Alarm flag

When all enabled comparisons first match, the alarm flag AF (register Control_2) is set.

AF remains set until cleared by command. Once AF has been cleared, it will only be set

again when the time increments to match the alarm condition once more. For clearing the

flags, see Section 8.10.5

Alarm registers which have their alarm enable bit AE_x at logic 1 are ignored.

8.10 Timer functions

The PCF2129 has a watchdog timer function. The timer can be switched on and off by

using the control bit WD_CD in the register Watchdg_tim_ctl.

The watchdog timer has four selectable source clocks. It can, for example, be used to

detect a microcontroller with interrupt and reset capability which is out of control (see

Section 8.10.3

)

To control the timer function and timer output, the registers Control_2, Watchdg_tim_ctl,

and Watchdg_tim_val are used.

Table 46. Weekday_alarm - weekday alarm register (address 0Eh) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit 7 6 5 4 3 2 1 0

Symbol AE_W - - - - WEEKDAY_ALARM (0 to 6)

Reset

value

1----XXX

Table 47. Weekday_alarm - weekday alarm register (address 0Eh) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit Symbol Value Description

7 AE_W 0 weekday alarm is enabled

1 weekday alarm is disabled

6 to 3 - - unused

2 to 0 WEEKDAY_ALARM 0 to 6 weekday alarm information

Example where only the minute alarm is used and no other interrupts are enabled.

Fig 18. Alarm flag timing diagram

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