Datasheet

PCF2129 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 19 December 2014 36 of 86
NXP Semiconductors
PCF2129
Accurate RTC with integrated quartz crystal for industrial applications
8.10.1 Register Watchdg_tim_ctl
8.10.2 Register Watchdg_tim_val
Table 48. Watchdg_tim_ctl - watchdog timer control register (address 10h) bit allocation
Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as T must always be written with logic 0.
Bit 7 6 5 4 3 2 1 0
Symbol WD_CD T TI_TP - - - TF[1:0]
Reset
value
000---11
Table 49. Watchdg_tim_ctl - watchdog timer control register (address 10h) bit description
Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as T must always be written with logic 0.
Bit Symbol Value Description
7 WD_CD 0 watchdog timer disabled
1 watchdog timer enabled;
the interrupt pin INT
is activated when timed out
6 T 0 unused
5 TI_TP 0 the interrupt pin INT
is configured to generate a
permanent active signal when MSF is set
1 the interrupt pin INT
is configured to generate a
pulsed signal when MSF flag is set (see Figure 21)
4 to 2 - - unused
1 to 0 TF[1:0] timer source clock for watchdog timer
00 4.096 kHz
01 64 Hz
10 1 Hz
11
1
⁄
60
Hz
Table 50. Watchdg_tim_val - watchdog timer value register (address 11h) bit allocation
Bits labeled as X are undefined at power-on and unchanged by subsequent resets.
Bit 7 6 5 4 3 2 1 0
Symbol WATCHDG_TIM_VAL[7:0]
Reset
value
XXXXXXXX
Table 51. Watchdg_tim_val - watchdog timer value register (address 11h) bit description
Bits labeled as X are undefined at power-on and unchanged by subsequent resets.
Bit Symbol Value Description
7to0 WATCHDG_TIM_
VAL[7:0]
00 to FF timer period in seconds:
where n is the timer value
TimerPeriod
n
SourceClockFrequency
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