Datasheet

PCF2129 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 19 December 2014 37 of 86
NXP Semiconductors
PCF2129
Accurate RTC with integrated quartz crystal for industrial applications
8.10.3 Watchdog timer function
The watchdog timer function is enabled or disabled by the WD_CD bit of the register
Watchdg_tim_ctl (see Table 49
).
The 2 bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock
frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or
1
⁄
60
Hz (see Table 52).
When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val
determines the watchdog timer period (see Table 52
).
The watchdog timer counts down from the software programmed 8-bit binary value n in
register Watchdg_tim_val. When the counter reaches 1, the watchdog timer flag WDTF
(register Control_2) is set logic 1 and an interrupt is generated.
The counter does not automatically reload.
When WD_CD is logic 0 (watchdog timer disabled) and the Microcontroller Unit (MCU)
loads a watchdog timer value n:
• the flag WDTF is reset
• INT is cleared
• the watchdog timer starts again
Loading the counter with 0 will:
• reset the flag WDTF
• clear INT
• stop the watchdog timer
Remark: WDTF is read only and cannot be cleared by command. WDTF can be cleared
by:
• loading a value in register Watchdg_tim_val
• reading of the register Control_2
Writing a logic 0 or logic 1 to WDTF has no effect.
Table 52. Programmable watchdog timer
TF[1:0] Timer source
clock frequency
Units Minimum timer
period (n = 1)
Units Maximum timer
period (n = 255)
Units
00 4.096 kHz 244 s 62.256 ms
01 64 Hz 15.625 ms 3.984 s
10 1 Hz 1 s 255 s
11
1
⁄
60
Hz 60 s 15300 s