Datasheet
PCF2129 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 19 December 2014 48 of 86
NXP Semiconductors
PCF2129
Accurate RTC with integrated quartz crystal for industrial applications
8.12.5 Timestamp interrupts
Interrupt generation from the timestamp function is controlled using the TSIE bit (register
Control_2). If TSIE is enabled, the INT
pin follows the status of the flags TSFx. Clearing
the flags TSFx immediately clears INT
. No pulse generation is possible for timestamp
interrupts.
8.12.6 Battery switch-over interrupts
Generation of interrupts from the battery switch-over is controlled by the BIE bit (register
Control_3). If BIE is enabled, the INT
pin follows the status of bit BF in register Control_3
(see Table 71
). Clearing BF immediately clears INT. No pulse generation is possible for
battery switch-over interrupts.
8.12.7 Battery low detection interrupts
Generation of interrupts from the battery low detection is controlled by the BLIE bit
(register Control_3). If BLIE is enabled, the INT
pin follows the status of bit BLF (register
Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when
bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared by
command.
8.13 External clock test mode
A test mode is available which allows on-board testing. In this mode, it is possible to set
up test conditions and control the operation of the RTC.
The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then
pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz)
with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT
generate an increment of one second.
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 25. AF timing diagram
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