Datasheet

PCF2129 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 19 December 2014 52 of 86
NXP Semiconductors
PCF2129
Accurate RTC with integrated quartz crystal for industrial applications
[1] The chip enable must not be wired permanently LOW.
9.1.1 Data transmission
The chip enable signal is used to identify the transmitted data. Each data transfer is a
whole byte, with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal SDA/CE
. The first
byte transmitted is the command byte. Subsequent bytes are either data to be written or
data to be read (see Figure 30
).
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The R/W
bit defines if the following
bytes are read or write information.
Table 75. Serial interface
Symbol Function Description
SDA/CE
chip enable input;
active LOW
[1]
when HIGH, the interface is reset;
input may be higher than V
DD
SCL serial clock input when SDA/CE is HIGH, input may float;
input may be higher than V
DD
SDI serial data input when SDA/CE is HIGH, input may float;
input may be higher than V
DD
;
input data is sampled on the rising edge of
SCL
SDO serial data output push-pull output;
drives from V
SS
to V
oper(int)
(V
BBS
);
output data is changed on the falling edge of
SCL
Fig 30. Data transfer overview
Table 76. Command byte definition
Bit Symbol Value Description
7R/W
data read or write selection
0 write data
1 read data
6 to 5 SA 01 subaddress;
other codes will cause the device to ignore
data transfer
4 to 0 RA 00h to 1Bh register address
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