Datasheet

PCF2129 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 19 December 2014 54 of 86
NXP Semiconductors
PCF2129
Accurate RTC with integrated quartz crystal for industrial applications
9.2 I
2
C-bus interface
The I
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are
connected to a positive supply by a pull-up resistor. Data transfer is initiated only when the
bus is not busy.
9.2.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line remains
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 33
).
9.2.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition P (see Figure 34
).
Remark: For the PCF2129, a repeated START is not allowed. Therefore a STOP has to
be released before the next START.
9.2.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves.
The PCF2129 can act as a slave transmitter and a slave receiver.
Fig 33. Bit transfer
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Fig 34. Definition of START and STOP conditions
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