Datasheet

PCF2129 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 19 December 2014 55 of 86
NXP Semiconductors
PCF2129
Accurate RTC with integrated quartz crystal for industrial applications
9.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I
2
C-bus is illustrated in Figure 36.
9.2.5 I
2
C-bus protocol
After a start condition, a valid hardware address has to be sent to a PCF2129 device. The
appropriate I
2
C-bus slave address is 1010001. The entire I
2
C-bus slave address byte is
shown in Table 77
.
Fig 35. System configuration
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2
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