Datasheet

PCF2129 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 19 December 2014 56 of 86
NXP Semiconductors
PCF2129
Accurate RTC with integrated quartz crystal for industrial applications
The R/W bit defines the direction of the following single or multiple byte data transfer (read
is logic 1, write is logic 0).
For the format and the timing of the START condition (S), the STOP condition (P), and the
acknowledge (A) refer to the I
2
C-bus specification Ref. 13 “UM10204” and the
characteristics table (Table 82
). In the write mode, a data transfer is terminated by sending
a STOP condition. A repeated START (Sr) condition is not applicable.
9.3 Bus communication and battery backup operation
To save power during battery backup operation (see Section 8.5.1), the bus interfaces are
inactive. Therefore the communication via I
2
C- or SPI-bus should be terminated before
the supply of the PCF2129 is switched from V
DD
to V
BAT
.
Remark: If the I
2
C-bus communication was terminated uncontrolled, the I
2
C-bus has to
be reinitialized by sending a STOP followed by a START after the device switched back
from battery backup operation to V
DD
supply operation.
Table 77. I
2
C slave address byte
Slave address
Bit 7 6 5 4 3 2 1 0
MSB LSB
1010001R/W
Fig 37. Bus protocol, writing to registers
DDD
6

WRQGDWDE\WHV
SOXV$&.
$ $ $3
6
VODYHDGGUHVV
ZULWHELW
UHJLVWHUDGGUHVV
KWR%K
DFNQRZOHGJH
IURP3&)
DFNQRZOHGJH
IURP3&)
DFNQRZOHGJH
IURP3&)
6723
67$5
7
Fig 38. Bus protocol, reading from registers
DDD
6
WRQGDWDE\WHV
SOXV$&.
'$7$%<7( /$67'$7$%<7(
UHDGELW
DFNQRZOHGJH
IURP3&)
$ $
6
VHWUHJLVWHU
DGGUHVV
UHDGUHJLVWHU
GDWD
ZULWHELW
$ $3
$3
QRDFNQRZOHGJH
DFNQRZOHGJH
IURPPDVWHU
6723
DFNQRZOHGJH
IURP3&)
DFNQRZOHGJH
IURP3&)
UHJLVWHUDGGUHVV
KWR%K
VODYHDGGUHVV
VODYHDGGUHVV