Datasheet

Product data sheet Rev. 3 — 11 July 2013 12 of 47

NXP Semiconductors

PCF85063TP

Tiny Real-Time Clock/calendar

[1] Default value.

For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1, each LSB

introduces an offset of 4.069 ppm. The values of 4.34 ppm and 4.069 ppm are based on a

nominal 32.768 kHz clock. The offset value is coded in two’s complement giving a range

of +63 LSB to 64 LSB.

[1] Default value.

The correction is made by adding or subtracting clock correction pulses, thereby changing

the period of a single second but not by changing the oscillator frequency.

It is possible to monitor when correction pulses are applied. To enable correction interrupt

generation, bit CIE (register Control_1) has to be set logic 1. At every correction cycle a

pulse is generated on pin INT

. The pulse width depends on the correction mode. If

multiple correction pulses are applied, an interrupt pulse is generated for each correction

pulse applied.

Table 12. Offset - offset register (address 02h) bit description

Bit Symbol Value Description

7MODE offset mode

[1]

normal mode: offset is made once every two

hours

1 course mode: offset is made every 4 minutes

6 to 0 OFFSET[6:0] see Table 13

offset value

Table 13. Offset values

OFFSET[6:0] Offset value in

decimal

Offset value in ppm

Normal mode

MODE = 0

Fast mode

MODE = 1

0111111 +63 +273.420 +256.347

0111110 +62 +269.080 +252.278

:: : :

0000010 +2 +8.680 +8.138

0000001 +1 +4.340 +4.069

0000000

[1]

1111111 1 4.340 4.069

1111110 2 8.680 8.138

:: : :

1000001 63 273.420 256.347

1000000 64 277.760 260.416