Datasheet

PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 July 2013 29 of 47
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
[1] For reliable oscillator start-up at power-on: V
DD(po)min
=V
DD(min)
+0.3V.
[2] Timer source clock =
1
⁄
60
Hz, level of pins SCL and SDA is V
DD
or V
SS
.
[3] Tested on sample basis.
[4] The I
2
C-bus interface of PCF85063TP is 5 V tolerant.
[5] Implicit by design.
[6] Integrated load capacitance, C
L(itg)
, is a calculation of C
OSCI
and C
OSCO
in series: .
Oscillator
f
osc
/f
osc
relative oscillator frequency
variation
V
DD
=200mV;
T
amb
=25C
- 0.075 - ppm
C
L(itg)
integrated load capacitance on pins OSCO, OSCI
[6]
C
L
= 7 pF 4.2 7 9.8 pF
C
L
= 12.5 pF 7.5 12.5 17.5 pF
R
s
series resistance - - 100 k
Table 31. Static characteristics
…continued
V
DD
= 0.9 V to 5.5 V; V
SS
=0V; T
amb
=  40  C to +85  C; f
osc
= 32.768 kHz; quartz R
s
=60k  ; C
L
= 7 pF; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
C
Litg
C
OSCI
C
OSCO

C
OSCI
C
OSCO
+
--------------------------------------------
=
T
amb
=25C; CLKOUT disabled.
(1) V
DD
=5.0V.
(2) V
DD
=3.3V.
Fig 20. Typical I
DD
with respect to f
SCL
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,
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