Datasheet
PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 July 2013 33 of 47
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
[1] A detailed description of the I
2
C-bus specification is given in Ref. 12 “UM10204”.
[2] I
2
C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
Table 32. I
2
C-bus characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +85
C; f
osc
= 32.768 kHz; quartz R
s
=60k
; C
L
= 7 pF; unless otherwise
specified. All timing values are valid within the operating supply voltage and temperature range and referenced to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
[1]
.
Symbol Parameter Conditions Min Typ Max Unit
C
b
capacitive load for each bus line - - 400 pF
f
SCL
SCL clock frequency
[2]
0- 400kHz
t
HD;STA
hold time (repeated) START
condition
0.6 - - s
t
SU;STA
set-up time for a repeated START
condition
0.6 - - s
t
LOW
LOW period of the SCL clock 1.3 - - s
t
HIGH
HIGH period of the SCL clock 0.6 - - s
t
r
rise time of both SDA and SCL
signals
20 + 0.1C
b
-0.3s
t
f
fall time of both SDA and SCL
signals
20 + 0.1C
b
-0.3s
t
BUF
bus free time between a STOP
and START condition
1.3 - - s
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
t
SU;STO
set-up time for STOP condition 0.6 - - s
t
VD;DAT
data valid time 0 - 0.9 s
t
VD;ACK
data valid acknowledge time 0 - 0.9 s
t
SP
pulse width of spikes that must be
suppressed by the input filter
0- 50ns
Fig 25. I
2
C-bus timing diagram; rise and fall times refer to 30 % and 70 %
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
013aaa417
t
SU;STO
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
1
/f
SCL
t
r
t
VD;DAT