Datasheet

PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 July 2013 46 of 47
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
26. Figures
Fig 1. Block diagram of PCF85063TP . . . . . . . . . . . . . . .2
Fig 2. Pin configuration for HWSON8 (PCF85063TP). . .3
Fig 3. Handling address registers . . . . . . . . . . . . . . . . . .4
Fig 4. STOP bit functional diagram . . . . . . . . . . . . . . . . .7
Fig 5. STOP bit release timing. . . . . . . . . . . . . . . . . . . . .8
Fig 6. Software reset command. . . . . . . . . . . . . . . . . . . .9
Fig 7. INT
example for MI . . . . . . . . . . . . . . . . . . . . . . .10
Fig 8. Offset calibration calculation workflow. . . . . . . . .15
Fig 9. Result of offset calibration . . . . . . . . . . . . . . . . . .16
Fig 10. OS flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Fig 11. Data flow for the time function . . . . . . . . . . . . . . .20
Fig 12. Access time for read/write operations . . . . . . . . .21
Fig 13. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Fig 14. Definition of START and STOP conditions. . . . . .22
Fig 15. System configuration . . . . . . . . . . . . . . . . . . . . . .23
Fig 16. Acknowledgement on the I
2
C-bus . . . . . . . . . . . .23
Fig 17. Master transmits to slave receiver
(WRITE mode). . . . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 18. Master reads after setting register address
(WRITE register address; READ data) . . . . . . . .25
Fig 19. Device diode protection diagram
of PCF85063TP . . . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 20. Typical I
DD
with respect to f
SCL
. . . . . . . . . . . . . .29
Fig 21. Typical I
DD
as a function of temperature . . . . . . .30
Fig 22. Typical I
DD
with respect to V
DD
. . . . . . . . . . . . . .31
Fig 23. I
DD
with respect to quartz R
S
. . . . . . . . . . . . . . . .32
Fig 24. Oscillator frequency variation with respect
to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Fig 25. I
2
C-bus timing diagram; rise and fall times
refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . .33
Fig 26. Application diagram for PCF85063TP . . . . . . . . .34
Fig 27. Package outline SOT1069-2 (HWSON8)
of PCF85063TP . . . . . . . . . . . . . . . . . . . . . . . . . .35
Fig 28. Tape and reel details for PCF85063TP . . . . . . . .36
Fig 29. Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Fig 30. Footprint information for reflow soldering
of SOT1069-2 (HWSON8) of PCF85063TP . . . .40