Datasheet

Product data sheet Rev. 6 — 17 September 2013 13 of 78

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

After reset, the following mode is entered:

• 32.768 kHz CLKOUT active

• 24 hour mode is selected

• Register Offset is set logic 0

• No alarms set

• Timers disabled

• No interrupts enabled

• Battery switch-over is disabled

• Battery low detection is disabled

• 7 pF of internal oscillator capacitor selected

8.4 Interrupt function

Active low interrupt signals are available at pin INT1/CLKOUT and INT2. Pin

INT1

/CLKOUT has both functions of INT1 and CLKOUT combined, that is that either the

CLKOUT or the INT1

can be used. Therefore the usage of INT1 requires that CLKOUT is

disabled.

INT1

Interrupt output may be sourced from different places:

• Second timer

• Timer A

• Timer B

• Alarm

• Battery switch-over

• Battery low detection

• Clock offset correction pulse

INT2

interrupt output is sourced only from timer B:

The control bit TAM (register Tmr_CLKOUT_ctrl) is used to configure whether the

interrupts generated from the second interrupt timer and timer A are pulsed signals or a

permanently active signal. The control bit TBM (register Tmr_CLKOUT_ctrl) is used to

configure whether the interrupt generated from timer B is a pulsed signal or a permanently

active signal. All the other interrupt sources generate a permanently active interrupt

signal, which follows the status of the corresponding flags.

• The flags SF, CTAF, CTBF, AF, and BSF can be cleared by using the interface

• WTAF is read only. Reading of the register Control_2 (01h) automatically resets

WTAF (WTAF = 0) and clears the interrupt

• The flag BLF is read only. It is cleared automatically from the battery low detection

circuit when the battery is replaced