Datasheet

Product data sheet Rev. 6 — 17 September 2013 26 of 78

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

When one or several alarm registers are loaded with a valid minute, hour, day, or weekday

value and its corresponding alarm enable bit (AEN_x) is logic 0, then that information is

compared with the current minute, hour, day, and weekday value. When all enabled

comparisons first match, the alarm flag, AF (register Control_2), is set logic 1.

The generation of interrupts from the alarm function is controlled via bit AIE (register

Control_1). If bit AIE is enabled, then the INT1

pin follows the condition of bit AF. AF

remains set until cleared by the interface. Once AF has been cleared, it will only be set

again when the time increments to match the alarm condition once more. Alarm registers,

which have their AEN_x bit logic 1 are ignored. The generation of interrupts from the

alarm function is described more detailed in Section 8.4

Table 26

and Table 27 show an example for clearing bit AF. Clearing the flag is made by a

write command, therefore bits 2, 1, and 0 must be re-written with their previous values.

Repeatedly re-writing these bits has no influence on the functional behavior.

To prevent the timer flags being overwritten while clearing bit AF, logic AND is performed

during a write access. A flag is cleared by writing logic 0 while a flag is not cleared by

writing logic 1. Writing logic 1 results in the flag value remaining unchanged.

Table 27 shows what instruction must be sent to clear bit AF. In this example, bit CTAF,

CTBF, and bit SF are unaffected.

[1] The bits labeled as - have to be rewritten with the previous values.

8.7.6 Alarm interrupts

Generation of interrupts from the alarm function is controlled via the bit AIE (register

Control_1). If AIE is enabled, the INT1

follows the status of bit AF (register Control_2).

Clearing AF immediately clears INT1

. No pulse generation is possible for alarm interrupts.

Example where only the minute alarm is used and no other interrupts are enabled.

Fig 16. Alarm flag timing

Table 26. Flag location in register Control_2

7 6 5 4 3 2 1 0

Control_2 WTAF CTAF CTBF SF AF - - -

Table 27. Example to clear only AF (bit 3)

[1]

7 6 5 4 3 2 1 0

Control_201110- - -

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