Datasheet

PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 17 September 2013 28 of 78
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
8.8 Register Offset
The PCF8523 incorporates an offset register (address 0Eh), which can be used to
implement several functions, like:
Aging adjustment
Temperature compensation
Accuracy tuning
[1] Default value.
For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1, each LSB
introduces an offset of 4.069 ppm. The values of 4.34 ppm and 4.069 ppm are based on a
nominal 32.768 kHz clock. The offset value is coded in two’s complement giving a range
of +63 LSB to 64 LSB.
[1] Default mode.
The correction is made by adding or subtracting clock correction pulses, thereby changing
the period of a single second.
It is possible to monitor when correction pulses are applied. To enable correction interrupt
generation, bit CIE (register Control_1) has to be set logic 1. At every correction cycle a
1
4096
s pulse is generated on pin INTx. If multiple correction pulses are applied, a
1
4096
s
interrupt pulse is generated for each correction pulse applied.
8.8.1 Correction when MODE = 0
The correction is triggered once per two hours and then correction pulses are applied
once per minute until the programmed correction values have been implemented.
Table 28. Offset - offset register (address 0Eh) bit description
Bit Symbol Value Description
7MODE 0
[1]
offset is made once every two hours
1 offset is made once every minute
6 to 0 OFFSET[6:0] see Table 29
offset value
Table 29. Offset values (in period time, not frequency)
OFFSET[6:0] Offset value in
decimal
Offset value in ppm
Every two hours
(MODE = 0)
Every minute
(MODE = 1)
0111111 +63 +273.420 +256.347
0111110 +62 +269.080 +252.278
::::
0000010 +2 +8.680 +8.138
0000001 +1 +4.340 +4.069
0000000 0
[1]
0
[1]
0
[1]
1111111 1 4.340 4.069
1111110 2 8.680 8.138
::::
1000001 63 273.420 256.347
1000000 64 277.760 260.416