Datasheet

PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 17 September 2013 33 of 78
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
[1] Duty cycle definition: % HIGH-level time : % LOW-level time.
[2] Default value.
[3] Clock frequencies may be affected by offset correction.
8.9.1.3 Register Tmr_A_freq_ctrl
[1] Default value.
8.9.1.4 Register Tmr_A_reg
[1] Timer period in seconds: where T_A is the countdown value.
Table 35. CLKOUT frequency selection
COF[2:0] CLKOUT frequency (Hz) Typical duty cycle
[1]
Effect of STOP bit
000
[2]
32768 60 : 40 to 40 : 60 no effect
001 16384 50 : 50 no effect
010 8192 50 : 50 no effect
011 4096 50 : 50 CLKOUT = high-Z
100 1024 50 : 50 CLKOUT = high-Z
101 32 50 : 50
[3]
CLKOUT = high-Z
110 1 50 : 50
[3]
CLKOUT = high-Z
111 CLKOUT disabled (high-Z)
Table 36. Tmr_A_freq_ctrl - timer A frequency control register (address 10h) bit
description
Bit Symbol Value Description
7 to 3 - - unused
2 to 0 TAQ[2:0] source clock for timer A (see Table 40
)
000 4.096 kHz
001 64 Hz
010 1 Hz
011
1
⁄
60
Hz
111
[1]
110
100
1
⁄
3600
Hz
Table 37. Tmr_A_reg - timer A value register (address 11h) bit description
Bit Symbol Value Description
7 to 0 T_A[7:0] 00 to FF
timer value
[1]
timerperiod
T_A
SourceClockFrequency
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