Datasheet

Product data sheet Rev. 6 — 17 September 2013 39 of 78

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

If a new value of T_B is written before the end of the actual timer-period, this value will

take immediate effect. It is not recommended to change T_B without first disabling the

counter by setting TBC logic 0 (register Tmr_CLKOUT_ctrl). The update of T_B is

asynchronous to the timer clock. Therefore changing it on the fly could result in a

corrupted value loaded into the countdown counter. This can result in an undetermined

countdown period for the first period. The countdown value T_B will be correctly stored

and correctly loaded on subsequent timer-periods.

Loading the counter with 0 effectively stops the timer.

When starting the countdown timer for the first time, only the first period does not have a

fixed duration. The amount of inaccuracy for the first timer-period depends on the chosen

source clock; see Table 41

When the interrupt generation is enabled (CTBIE = 1) and the countdown timer flag CTAF

is set logic 1, interrupt signals on INT1

and INT2 are generated. The interrupt may be

generated as a pulsed signal every countdown period or as a permanently active signal,

which follows the condition of CTBF (register Control_2). The TBM bit (register

Tmr_CLKOUT_ctrl) is used to control this mode selection. Interrupt output may be

disabled with the CTBIE bit (register Control_2).

8.9.4 Second interrupt timer

PCF8523 has a pre-defined timer, which is used to generate an interrupt once per second.

The pulse generator for the second interrupt timer operates from an internal 64 Hz clock

and generates a pulse of

⁄

s in duration. It is independent of the watchdog or countdown

timer and can be switched on and off by the SIE bit in register Control_1 (00h).

The interrupt generated by the second interrupt timer may be generated as pulsed signal

every second or as a permanently active signal. The TAM bit (register Tmr_CLKOUT_ctrl)

is used to control the interrupt generation mode.

When the second interrupt timer is enabled (SIE = 1), then the timer sets the flag SF

(register Control_2) every second (see Table 42

). SF may only be cleared by using the

interface. Instructions, how to clear a flag, are given in Section 8.7.5

When SF is logic 1:

• If TAM (register Tmr_CLKOUT_ctrl) is logic 1, the interrupt is generated as a pulsed

signal every second

• If TAM is logic 0, the interrupt is a permanently active signal that remains, until SF is

cleared

Table 42. Effect of bit SIE on INT1 and bit SF

SIE Result on INT1 Result on SF

0 no interrupt generated SF never set

1 an interrupt once per second SF set when seconds counter increments