Datasheet

PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 17 September 2013 40 of 78
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
8.9.5 Timer interrupt pulse
The timer interrupt is generated as a pulsed signal when TAM or TBM are set logic 1. The
pulse generator for the timer interrupt also uses an internal clock, but this time it is
dependent on the selected source clock for the timer and on the timer register value T_x.
So, the width of the interrupt pulse varies; see Table 43
and Table 44.
[1] T_A = loaded timer register value. Timer stops when T_A = 0.
For timer B, interrupt pulse width is programmable via bit TBM (register
Tmr_CLKOUT_ctrl).
In this example, bit TAM is set logic 1 and the SF flag is not cleared after an interrupt.
Fig 22. Example for second interrupt when TAM = 1
In this example, bit TAM is set logic 0 and the SF flag is cleared after an interrupt.
Fig 23. Example for second interrupt when TAM = 0
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PLQXWHVFRXQWHU
,17ZKHQ6,(HQDEOHG
6)ZKHQ6,(HQDEOHG

 
DDD
VHFRQGVFRXQWHU
PLQXWHVFRXQWHU
,17ZKHQ6,(HQDEOHG
6)ZKHQ6,(HQDEOHG
 

  
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Table 43. Interrupt low pulse width for timer A
Pulse mode, bit TAM set logic 1.
Source clock (Hz) Interrupt pulse width
T_A = 1
[1]
T_A > 1
[1]
4096 122 s 244 s
64 7.812 ms 15.625 ms
1 15.625 ms 15.625 ms
1
⁄
60
15.625 ms 15.625 ms
1
⁄
3600
15.625 ms 15.625 ms