Datasheet
PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 17 September 2013 41 of 78
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
[1] T_B = loaded timer register value. Timer stops when T_B = 0.
[2] If pulse period is shorter than the setting via bit TBW[2:0], the interrupt pulse width is set to 15.625 ms.
When flags like SF, CTAF, WTAF, and CTBF are cleared before the end of the interrupt
pulse, then the interrupt pulse is shortened. This allows the source of a system interrupt to
be cleared immediately when it is serviced, that is, the system does not have to wait for
the completion of the pulse before continuing; see Figure 24
and Figure 25. Instructions
for clearing flags can be found in Section 8.7.5
. Instructions for clearing the bit WTAF can
be found in Section 8.9.2.1
.
Table 44. Interrupt low pulse width for timer B
Pulse mode, bit TBM set logic 1.
Source clock (Hz). Interrupt pulse width
T_B = 1
[1]
T_B > 1
[1]
4096 122 s 244 s
64 7.812 ms see Table 38
[2]
1 see Table 38 :
1
⁄
60
::
1
⁄
3600
::
(1) Indicates normal duration of INT1 pulse.
The timing shown for clearing bit SF is also valid for the non-pulsed interrupt mode, that is, when
TAM set logic 0, where the INT1
pulse may be shortened by setting SIE logic 0.
Fig 24. Example of shortening the INT1 pulse by clearing the SF flag
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