Datasheet
PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 17 September 2013 44 of 78
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
[1] F
0
is clocked at 32.768 kHz.
8.11 I
2
C-bus interface
The I
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are
connected to a positive supply via a pull-up resistor. Data transfer is initiated only when
the bus is not busy.
8.11.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line remains
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 28
).
Table 45. First increment of time circuits after STOP release
Bit Prescaler bits
[1]
1Hz tick Time Comment
STOP F
0
F
1
-F
2
to F
14
hh:mm:ss
Clock is running normally
0
01-0000111010100
12:45:12 prescaler counting normally
STOP is activated by user; F
0
F
1
are not reset and values cannot be predicted externally
1
XX-0000000000000
12:45:12 prescaler is reset; time circuits are frozen
New time is set by user
1
XX-0000000000000
08:00:00 prescaler is reset; time circuits are frozen
STOP is released by user
0
XX-0000000000000
08:00:00 prescaler is now running
0
XX-1000000000000
08:00:00 -
0
XX-0100000000000
08:00:00 -
0
XX-1100000000000
08:00:00 -
:: : :
0
11-1111111111110
08:00:00 -
0
00-0000000000001
08:00:01 0 to 1 transition of F14 increments the time circuits
0
10-0000000000001
08:00:01 -
:: : :
0
11-1111111111111
08:00:01 -
0
00-0000000000000
08:00:01 -
:: : :
0
11-1111111111110
08:00:01 -
0
00-0000000000001
08:00:02 0 to 1 transition of F14 increments the time circuits
DDD
VWRV
V