Datasheet

PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 17 September 2013 46 of 78
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
8.11.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge cycle after the
reception of each byte
• Also a master receiver must generate an acknowledge cycle after the reception of
each byte that has been clocked out of the slave transmitter
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the related
acknowledge clock pulse (set-up and hold times must be considered)
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge cycle on the last byte that has been clocked out of the slave. In this
event, the transmitter must leave the data line HIGH to enable the master to generate
a STOP condition
Acknowledgement on the I
2
C-bus is shown in Figure 31.
8.11.5 I
2
C-bus protocol
One I
2
C-bus slave address (1101000) is reserved for the PCF8523. The entire I
2
C-bus
slave address byte is shown in Table 46
.
[1] Devices with other I
2
C-bus slave addresses can be produced on request.
After a START condition, the I
2
C slave address has to be sent to the PCF8523 device.
Fig 31. Acknowledgement on the I
2
C-bus
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Table 46. I
2
C slave address byte
Slave address
[1]
Bit 7 6 5 4 3 2 1 0
MSB LSB
1101000R/W