Datasheet

PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 17 September 2013 50 of 78
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
12. Static characteristics
Table 48. Static characteristics
V
DD
= 1.2 V to 5.5 V; V
SS
=0V; T
amb
=  40  C to +85  C; f
osc
= 32.768 kHz; quartz R
s
=40k  ; C
L
= 7 pF; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DD
supply voltage I
2
C-bus inactive;
for clock data integrity
T
amb
= 40 C to +85 C
[1]
1.2- 5.5V
T
amb
=+10C to +85 C
[2]
1.0- 5.5V
I
2
C-bus active 1.6 - 5.5 V
power management function active 1.8 - 5.5 V
SR
f
falling slew rate of V
DD
[3]
--0.5V/ms
V
BAT
battery supply voltage power management function active 1.8 - 5.5 V
I
DD
supply current I
2
C-bus active;
f
SCL
= 1000 kHz
- - 200 A
I
2
C-bus inactive (f
SCL
=0Hz);
interrupts disabled
clock-out disabled;
power management function disabled
(PM[2:0] = 111)
T
amb
=25C;
V
DD
=3.0V
[4]
-150-nA
T
amb
= 40 C to +85 C;
V
DD
= 2.0 V to 5.0 V
[4]
- - 500 nA
clock-out enabled at 32 kHz;
power management function enabled
(PM[2:0] = 000)
T
amb
=25C;
V
BAT
or V
DD
=3.0V
[5]
-1200-nA
T
amb
= 40 C to +85 C;
V
BAT
or V
DD
= 2.0 V to 5.0 V
[5]
- - 3600 nA
I
L(bat)
battery leakage current V
DD
active; V
BAT
= 3.0 V - 50 100 nA
Power management
V
th(sw)bat
battery switch threshold
voltage
2.12.52.7V
Inputs
[6]
V
IL
LOW-level input voltage - - 0.3V
DD
V
V
IH
HIGH-level input
voltage
0.7V
DD
--V
V
I
input voltage 0.5 - V
DD
+0.5 V
I
LI
input leakage current V
I
= V
SS
or V
DD
-0-nA
post ESD event 1- +1A
C
I
input capacitance
[7]
--7pF