Datasheet

PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 17 September 2013 51 of 78
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
[1] For reliable oscillator start at power-up: V
DD
=V
DD(min)
+0.3V.
[2] For reliable oscillator start at power-up: V
DD
=V
DD(min)
+0.5V.
[3] Switching the supply from V
DD
to V
BAT
must be made slower than the specified slew rate.
[4] Timer source clock =
1
⁄
3600
Hz, level of pins SCL and SDA is V
DD
or V
SS
.
[5] When the device is supplied via the V
BAT
pin instead of the V
DD
pin, the current values for I
BAT
will be as specified for I
DD
under the same
conditions.
[6] The I
2
C-bus is 5 V tolerant.
[7] Implicit by design.
[8] Tested on sample basis.
[9] Integrated load capacitance, C
L(itg)
, is a calculation of C
OSCI
and C
OSCO
in series: .
[10] Tested at 25 C.
[11] Crystal characteristic specification.
Outputs
V
O
output voltage on pins INT1/CLKOUT, CLKOUT, INT2,
SDA (refers to external pull-up voltage)
0.5 - 5.5 V
V
OL
LOW-level output
voltage
V
SS
-0.4V
I
OL
LOW-level output
current
output sink current;
on pins INT1/CLKOUT, CLKOUT, INT2;
V
OL
=0.4V; V
DD
=5V
[8]
1.5 - - mA
on pin SDA
V
OL
=0.4V; V
DD
=3.0V
[8]
20 - - mA
I
LO
output leakage current V
O
=V
SS
or V
DD
-0-nA
post ESD event 1- +1A
C
L(itg)
integrated load
capacitance
on pins OSCO, OSCI
[9][1
0]
C
L
= 7 pF 3.3 7 14 pF
C
L
= 12.5 pF 6 12.5 25 pF
R
S
series resistance
[11]
- - 100 k
Table 48. Static characteristics …continued
V
DD
= 1.2 V to 5.5 V; V
SS
=0V; T
amb
=  40  C to +85  C; f
osc
= 32.768 kHz; quartz R
s
=40k  ; C
L
= 7 pF; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
C
Litg
C
OSCI
C
OSCO

C
OSCI
C
OSCO
+
--------------------------------------------
=