Datasheet

PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 17 September 2013 75 of 78
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
27. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. PCF8523U wafer information . . . . . . . . . . . . . . .2
Table 4. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 5. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 6. Registers overview . . . . . . . . . . . . . . . . . . . . . .7
Table 7. Control_1 - control and status register 1
(address 00h) bit description . . . . . . . . . . . . . . .9
Table 8. Control_2 - control and status register 2
(address 01h) bit description . . . . . . . . . . . . . .10
Table 9. Control_3 - control and status register 3
(address 02h) bit description . . . . . . . . . . . . . .11
Table 10. Register reset values . . . . . . . . . . . . . . . . . . . .12
Table 11. Power management function control bits . . . . .15
Table 12. Seconds - seconds and clock integrity status
register (address 03h) bit description . . . . . . . .20
Table 13. SECONDS coded in BCD format . . . . . . . . . . .20
Table 14. Minutes - minutes register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 15. Hours - hours register (address 05h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 16. Days - days register (address 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 17. Weekdays - weekdays register
(address 07h) bit description . . . . . . . . . . . . . .22
Table 18. Weekday assignments . . . . . . . . . . . . . . . . . . .22
Table 19. Months - months register (address 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 20. Month assignments in BCD format. . . . . . . . . .22
Table 21. Years - years register (09h) bit description. . . .23
Table 22. Minute_alarm - minute alarm register
(address 0Ah) bit description . . . . . . . . . . . . . .24
Table 23. Hour_alarm - hour alarm register
(address 0Bh) bit description . . . . . . . . . . . . . .24
Table 24. Day_alarm - day alarm register
(address 0Ch) bit description . . . . . . . . . . . . . .25
Table 25. Weekday_alarm - weekday alarm register
(address 0Dh) bit description . . . . . . . . . . . . . .25
Table 26. Flag location in register Control_2 . . . . . . . . . .26
Table 27. Example to clear only AF (bit 3) . . . . . . . . . . . .26
Table 28. Offset - offset register (address 0Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 29. Offset values (in period time, not frequency) . .28
Table 30. Correction pulses for MODE = 0. . . . . . . . . . . .29
Table 31. Effect of clock correction for MODE = 0 . . . . . .29
Table 32. Correction pulses for MODE = 1 . . . . . . . . . . .30
Table 33. Effect of clock correction for MODE = 1 . . . . .30
Table 34. Tmr_CLKOUT_ctrl - timer and CLKOUT
control register (address 0Fh) bit description .32
Table 35. CLKOUT frequency selection . . . . . . . . . . . . .33
Table 36. Tmr_A_freq_ctrl - timer A frequency control
register (address 10h) bit description . . . . . . .33
Table 37. Tmr_A_reg - timer A value register
(address 11h) bit description. . . . . . . . . . . . . . .33
Table 38. Tmr_B_freq_ctrl - timer B frequency control
register (address 12h) bit description . . . . . . .34
Table 39. Tmr_B_reg - timer B value register
(address 13h) bit description . . . . . . . . . . . . . . 34
Table 40. Programmable timer characteristics . . . . . . . . 34
Table 41. First period delay for timer counter value T_A 37
Table 42. Effect of bit SIE on INT1
and bit SF . . . . . . . . . 39
Table 43. Interrupt low pulse width for timer A. . . . . . . . . 40
Table 44. Interrupt low pulse width for timer B. . . . . . . . . 41
Table 45. First increment of time circuits after STOP
release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 46. I
2
C slave address byte. . . . . . . . . . . . . . . . . . . 46
Table 47. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 48. Static characteristics . . . . . . . . . . . . . . . . . . . . 50
Table 49. I
2
C-bus interface timing . . . . . . . . . . . . . . . . . . 52
Table 50. Dimensions of PCF8523U . . . . . . . . . . . . . . . . 59
Table 51. Bump locations . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 52. Alignment mark dimension and location . . . . . 60
Table 53. Gold bump hardness of PCF8523U. . . . . . . . . 60
Table 54. Carrier tape dimensions of PCF8523 . . . . . . . 61
Table 55. SnPb eutectic process (from J-STD-020C) . . . 65
Table 56. Lead-free process (from J-STD-020C) . . . . . . 65
Table 57. Selection of Real-Time Clocks . . . . . . . . . . . . 68
Table 58. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 59. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 72