Datasheet

PCF8563 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 3 April 2012 22 of 50
NXP Semiconductors
PCF8563
Real-time clock/calendar
8.11 Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I
2
C-bus logic is initialized including the address pointer and
all registers are set according to Table 27
. I
2
C-bus communication is not possible during
reset.
[1] Registers marked x are undefined at power-up and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I
2
C-bus pins, SDA and SCL, are toggled in a specific order as
shown in Figure 13
. All timings are required minimums.
Once the override mode has been entered, the device immediately stops, being reset,
and normal operation may commence i.e. entry into the EXT_CLK test mode via I
2
C-bus
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0
during normal operation has no effect except to prevent entry into the POR override
mode.
Table 27. Register reset value
[1]
Address Register name Bit
7 6 5 4 3 2 1 0
00h Control_status_100001000
01h Control_status_200000000
02h VL_seconds 1xxxxxxx
03h Minutes xxxxxxxx
04h Hours xxxxxxxx
05h Days xxxxxxxx
06h Weekdays xxxxxxxx
07h Century_monthsxxxxxxxx
08h Years xxxxxxxx
09h Minute_alarm 1xxxxxxx
0AhHour_alarm 1xxxxxxx
0BhDay_alarm 1xxxxxxx
0ChWeekday_alarm1xxxxxxx
0DhCLKOUT_control1xxxxx00
0EhTimer_control 0xxxxx11
0FhTimer xxxxxxxx