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1. Product proﬁle

1.1 General description

500 mA, 50 V NPN/PNP double Resistor-Equipped Transistor (RET) in a small

SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package.

NPN/NPN complement: PIMN31

1.2 Features

n 500 mA output current capability

n Built-in bias resistors

n Simpliﬁes circuit design

n Reduces component count

n Reduces pick and place costs

n AEC-Q101 qualiﬁed

1.3 Applications

n Digital application in automotive and industrial segments

n Switching loads

1.4 Quick reference data

PIMC31

500 mA, 50 V NPN/PNP double resistor-equipped transistor;

R1 = 1 kΩ, R2 = 10 kΩ

Rev. 01 — 24 March 2009 Product data sheet

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

Per transistor; for the PNP transistor with negative polarity

CEO

collector-emitter voltage open base - - 50 V

output current - - 500 mA

R1 bias resistor 1 (input) 0.7 1 1.3 kΩ

R2/R1 bias resistor ratio 9 10 11

Summary of content (13 pages)

PAGE 1
PIMC31 500 mA, 50 V NPN/PNP double resistor-equipped transistor; R1 = 1 kΩ, R2 = 10 kΩ Rev. 01 — 24 March 2009 Product data sheet 1. Product profile 1.1 General description 500 mA, 50 V NPN/PNP double Resistor-Equipped Transistor (RET) in a small SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package. NPN/NPN complement: PIMN31 1.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 2. Pinning information Table 2. Pinning Pin Description Simplified outline 1 GND (emitter) TR1 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 5 input (base) TR2 6 output (collector) TR1 6 5 4 1 2 3 Graphic symbol 6 5 R1 4 R2 TR2 TR1 R2 1 R1 2 3 006aaa143 3. Ordering information Table 3.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 006aaa494 103 Zth(j-a) (K/W) δ=1 0.75 0.50 0.33 102 0.20 0.10 0.05 10 0.02 0.01 0 1 10−5 10−4 10−3 10−2 10−1 1 102 10 103 tp (s) FR4 PCB, standard footprint Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 7. Characteristics Table 7. Characteristics Tamb = 25 °C unless otherwise specified.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 006aaa314 103 (1) (1) (2) (3) hFE 006aaa315 10−1 (2) (3) VCEsat (V) 102 10 1 10−1 1 10 102 10−2 103 10 1 VCE = 5 V IC/IB = 20 (1) Tamb = 100 °C (1) Tamb = 100 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = −40 °C (3) Tamb = −40 °C Fig 3. 102 103 IC (mA) IC (mA) TR1 (NPN): DC current gain as a function of collector current; typical values Fig 4.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 006aaa316 10 006aaa317 1 (1) (2) VI(off) (V) VI(on) (V) 1 (3) (1) (2) (3) 10−1 10−1 1 10 102 103 10−1 10−1 VCE = 0.3 V (1) Tamb = −40 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = 100 °C (3) Tamb = 100 °C TR1 (NPN): On-state input voltage as a function of collector current; typical values Fig 7.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 006aaa349 103 006aaa350 −10−1 (1) hFE (1) (2) (2) (3) VCEsat (V) (3) 102 10 1 −10−1 −1 −10 −102 −10−2 −103 −1 −10 VCE = −5 V IC/IB = 20 (1) Tamb = 100 °C (1) Tamb = 100 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = −40 °C (3) Tamb = −40 °C Fig 8. −103 −102 IC (mA) IC (mA) TR2 (PNP): DC current gain as a function of collector current; typical values Fig 9.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 006aaa351 −10 006aaa352 −10 VI(off) (V) VI(on) (V) (1) (1) (2) −1 −10−1 −10−1 −1 (2) −1 (3) −10 −102 −103 (3) −10−1 −10−1 IC (mA) −10 IC (mA) VCE = −0.3 V VCE = −5 V (1) Tamb = −40 °C (1) Tamb = −40 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = 100 °C (3) Tamb = 100 °C Fig 11. TR2 (PNP): On-state input voltage as a function of collector current; typical values Fig 12.
PAGE 9
PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline 3.1 2.7 6 3.0 2.5 1.7 1.3 1.1 0.9 5 4 2 3 0.6 0.2 pin 1 index 1 0.40 0.25 0.95 0.26 0.10 1.9 Dimensions in mm 04-11-08 Fig 13.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 11. Soldering 3.45 1.95 0.45 0.55 (6×) (6×) 0.95 solder lands solder resist 3.3 2.825 0.95 solder paste occupied area 0.7 (6×) Dimensions in mm 0.8 (6×) 2.4 sot457_fr Fig 14. Reflow soldering footprint SOT457 (SC-74) 5.3 1.5 (4×) solder lands 1.475 0.45 (2×) 5.05 solder resist occupied area 1.475 Dimensions in mm preferred transport direction during soldering 1.45 (6×) 2.85 sot457_fw Fig 15.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PIMC31_1 20090324 Product data sheet - - PIMC31_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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PIMC31 NXP Semiconductors 500 mA, 50 V NPN/PNP double RET; R1 = 1 kΩ, R2 = 10 kΩ 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . .