Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsPN5120A0HN1/C1,151

1. Introduction

This document describes the functionality and electrical specifications of the

transceiver IC PN512.

The PN512 is a highly integrated transceiver IC for contactless communication at

13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation

concept completely integrated for different kinds of contactless communication methods

and protocols at 13.56 MHz.

1.1 Different available versions

The PN512 is available in three versions:

• PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2

(TFBGA64), hereafter named as version 2.0

• PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In),

hereafter named as industrial version, fulfilling the automotive qualification stated in

AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical

stress test qualification for automotive integrated circuits (ICs).

• PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named

as version 1.0

The data sheet describes the functionality for the industrial version and version 2.0. The

differences of the version 1.0 to the version 2.0 are summarized in Section 21

. The

industrial version has only differences within the outlined characteristics and limitations.

2. General description

The PN512 transceiver ICs support 4 different operating modes

• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• Reader/Writer mode supporting ISO/IEC 14443B

• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• NFCIP-1 mode

Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal

transmitter part is able to drive a reader/writer antenna designed to communicate with

ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The

receiver part provides a robust and efficient implementation of a demodulation and

PN512

Full NFC Forum compliant solution

Rev. 4.6 — 2 December 2014

111346

Product data sheet

COMPANY PUBLIC

Summary of content (136 pages)

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PN512 Full NFC Forum compliant solution Rev. 4.6 — 2 December 2014 111346 Product data sheet COMPANY PUBLIC 1. Introduction This document describes the functionality and electrical specifications of the transceiver IC PN512. The PN512 is a highly integrated transceiver IC for contactless communication at 13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz. 1.
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PN512 NXP Semiconductors Full NFC Forum compliant solution decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection (Parity & CRC). The PN512 supports MIFARE 1K or MIFARE 4K emulation products. The PN512 supports contactless communication using MIFARE higher transfer speeds up to 424 kbit/s in both directions.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 3.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions VDDA analog supply voltage VDDD digital supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V Min Typ Max Unit [1][2] 2.5 - 3.6 V [3] 1.6 - 3.6 V 1.6 - 3.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 5. Ordering information Table 2. Ordering information Type number Package Name Description Version PN5120A0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN/C2 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6  6  0.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 6. Block diagram The analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin.
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PN512 NXP Semiconductors Full NFC Forum compliant solution D6/ADR_0/ D4/ADR_2 MOSI/MX D5/ADR_1/ D7/SCL/ D3/ADR_3 SCK/DTRQ MISO/TX D2/ADR_4 SDA/NSS/RX EA 24 I2C 32 D1/ADR_5 1 25 27 26 30 29 28 PVDD PVSS 2 31 5 3 VOLTAGE MONITOR AND POWER ON DETECT SPI, UART, I2C-BUS INTERFACE CONTROL 4 15 18 FIFO CONTROL DVDD DVSS AVDD AVSS STATE MACHINE 64-BYTE FIFO BUFFER COMMAND REGISTER RESET CONTROL PROGRAMABLE TIMER POWER-DOWN CONTROL CONTROL REGISTER BANK 6 23 INTERRUPT CONTROL MIFARE
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PN512 NXP Semiconductors Full NFC Forum compliant solution 7. Pinning information 25 D1 26 D2 27 D3 28 D4 29 D5 30 D6 32 A0 terminal 1 index area 31 D7 7.
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PN512 NXP Semiconductors Full NFC Forum compliant solution ball A1 index area TFBGA64 1 2 3 4 5 6 7 8 A B C D E F G H aaa-005873 Transparent top view Fig 5. PN512 Product data sheet COMPANY PUBLIC Pin configuration TFBGA64 (SOT1336-1) All information provided in this document is subject to legal disclaimers. Rev. 4.6 — 2 December 2014 111346 © NXP Semiconductors N.V. 2014. All rights reserved.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 7.2 Pin description Table 3. Pin description HVQFN32 Pin Symbol Type Description 1 A1 I Address Line 2 PVDD PWR Pad power supply 3 DVDD PWR Digital Power Supply 4 DVSS PWR Digital Ground 5 PVSS PWR Pad power supply ground 6 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 4. Pin description HVQFN40 Pin Symbol Type Description 1 to 4 A2 to A5 I Address Line 5 PVDD PWR Pad power supply 6 DVDD PWR Digital Power Supply 7 DVSS PWR Digital Ground 8 PVSS PWR Pad power supply ground 9 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 5. Pin description TFBGA64 Pin Symbol Type Description A1 to A5, A8, B3, B4, B8, E1 PVSS PWR Pad power supply ground A6 D4 I/O 8-bit Bi-directional Data Bus. A7 D2 I/O Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 5. Pin description TFBGA64 Pin Symbol Type Description H4 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 H5 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier H7 AVDD PWR Analog Power Supply PN512 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.6 — 2 December 2014 111346 © NXP Semiconductors N.V. 2014.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 8. Functional description The PN512 transmission module supports the Read/Write mode for ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and modulation protocols.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer …continued Communication direction Signal type Card to reader (PN512 receives data from a card) Transfer speed 106 kBd 212 kBd 424 kBd card side modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 8.3 FeliCa reader/writer functionality The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters. 1. PCD to PICC, 8-30 % ASK Manchester coded, baudrate 212 to 424 kbaud Felica READER (PCD) FeliCa CARD (PICC) PN512 2.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 8.4 NFCIP-1 mode The NFCIP-1 communication differentiates between an active and a Passive Communication mode. • Active Communication mode means both the initiator and the target are using their own RF field to transmit data. • Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active in terms of generating the RF field. • Initiator: generates RF field at 13.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 8.4.1 Active communication mode Active communication mode means both the initiator and the target are using their own RF field to transmit data. Initial command host NFC INITIATOR powered to generate RF field NFC TARGET 1. initiator starts communication at selected transfer speed host powered for digital processing response host NFC INITIATOR NFC TARGET 2.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 8.4.2 Passive communication mode Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field. 1. initiator starts communication at selected transfer speed host NFC TARGET NFC INITIATOR 2.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 8.4.3 NFCIP-1 framing and coding The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard. Table 12. Framing and coding overview Transfer speed Framing and Coding 106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme 212 kbit/s According to the FeliCa scheme 424 kbit/s According to the FeliCa scheme 8.4.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 8.4.6 FeliCa Card operation mode Table 14. FeliCa Card operation mode Communication direction reader/writer  PN512 FeliCa FeliCa Higher transfer speeds Transfer speed 212 kbit/s 424 kbit/s Modulation on reader side 8-30 % ASK 8-30 % ASK bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 15.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 15. PN512 registers overview …continued Addr (hex) Register Name Function 7 VersionReg Shows the version 8 AnalogTestReg Controls the pins AUX1 and AUX2 9 TestDAC1Reg Defines the test value for the TestDAC1 A TestDAC2Reg Defines the test value for the TestDAC2 B TestADCReg Shows the actual value of ADC I and Q C-F RFT Reserved for production tests 9.1.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2 Register description 9.2.1 Page 0: Command and status 9.2.1.1 PageReg Selects the register page. Table 17. PageReg register (address 00h); reset value: 00h, 0000000b 7 6 5 4 3 2 1 UsePage Select 0 0 0 0 0 PageSelect r/w RFU RFU RFU RFU RFU Access Rights Table 18.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.3 CommIEnReg Control bits to enable and disable the passing of interrupt requests. Table 21. Access Rights Table 22.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.4 DivIEnReg Control bits to enable and disable the passing of interrupt requests. Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b 7 6 5 IRQPushPull 0 0 r/w RFU RFU Access Rights 4 3 2 1 SiginActIEn ModeIEn CRCIEn RFOnIEn r/w r/w r/w r/w 0 RFOffIEn r/w Table 24. Description of DivIEnReg bits Bit Symbol Description 7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.5 CommIRqReg Contains Interrupt Request bits. Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b 7 6 5 4 Set1 TxIRq RxIRq IdleIRq w dy dy dy Access Rights 3 2 HiAlertIRq LoAlertIRq dy dy 1 0 ErrIRq TimerIRq dy dy Table 26. Description of CommIRqReg bits All bits in the register CommIRqReg shall be cleared by software.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.6 DivIRqReg Contains Interrupt Request bits Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb 7 6 5 Set2 0 0 w RFU RFU Access Rights 4 3 SiginActIRq ModeIRq dy dy 2 1 0 CRCIRq RFOnIRq RFOffIRq dy dy dy Table 28. Description of DivIRqReg bits All bits in the register DivIRqReg shall be cleared by software.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.7 ErrorReg Error bit register showing the error status of the last command executed. Table 29. Access Rights ErrorReg register (address 06h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr r r r r r r r r Table 30.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.8 Status1Reg Contains status bits of the CRC, Interrupt and FIFO-buffer. Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb 7 6 5 RFFreqOK CRCOk CRCReady Access Rights r r r 4 3 2 1 0 IRq TRunning RFOn HiAlert LoAlert r r r r r Table 32. Description of Status1Reg bits Bit Symbol Description 7 RFFreqOK Indicates if the frequency detected at the RX pin is in the range of 13.56 MHz.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.9 Status2Reg Contains status bits of the Receiver, Transmitter and Data mode detector. Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b 7 6 5 TempSensClear I2CForceHS 0 r/w r/w RFU Access Rights Table 34.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.10 FIFODataReg In- and output of 64 byte FIFO-buffer. Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 dy dy dy dy FIFOData Access Rights 9.2.1.11 dy dy dy dy Table 36. Description of FIFODataReg bits Bit Symbol Description 7 to 0 FIFOData Data input and output port for the internal 64 byte FIFO-buffer.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.12 WaterLevelReg Defines the level for FIFO under- and overflow warning. Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b Access Rights 7 6 5 0 0 RFU RFU 4 3 2 1 0 r/w r/w WaterLevel r/w r/w Table 40. Description of WaterLevelReg bits Bit Symbol r/w r/w Description 7 to 6 - Reserved for future use.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.14 BitFramingReg Adjustments for bit oriented frames. Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b 7 6 StartSend Access Rights w 5 4 RxAlign r/w r/w 3 2 0 r/w Table 44. Description of BitFramingReg bits Bit Symbol 7 StartSend RFU 1 0 TxLastBits r/w r/w r/w Description Set to logic 1, the transmission of data starts. This bit is only valid in combination with the Transceive command.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.1.15 CollReg Defines the first bit collision detected on the RF interface. Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb 7 6 5 Values AfterColl 0 CollPos NotValid r/w RFU r Access Rights Table 46. 4 3 2 1 0 r r CollPos r r r Description of CollReg bits Bit Symbol Description 7 ValuesAfterColl If this bit is set to logic 0, all receiving bits will be cleared after a collision.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2 Page 1: Communication 9.2.2.1 PageReg Selects the register page. Table 47. PageReg register (address 10h); reset value: 00h, 00000000b 7 6 5 4 3 2 UsePage Select 0 0 0 0 0 r/w RFU RFU RFU RFU RFU Access Rights Table 48. 1 0 PageSelect r/w r/w Description of PageReg bits Bit Symbol Description 7 UsePage Select Set to logic 1, the value of PageSelect is used as register address A5 and A4.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.2 ModeReg Defines general mode settings for transmitting and receiving. Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b 7 6 5 4 3 2 MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff Access Rights r/w r/w r/w r/w r/w r/w 1 0 CRCPreset r/w r/w Table 50.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.3 TxModeReg Defines the data rate and framing during transmission. Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b 7 6 TxCRCEn Access Rights Table 52. r/w 5 4 TxSpeed dy dy 3 2 InvMod TxMix r/w r/w dy 1 0 TxFraming dy dy Description of TxModeReg bits Bit Symbol Description 7 TxCRCEn Set to logic 1, this bit enables the CRC generation during data transmission.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.4 RxModeReg Defines the data rate and framing during reception. Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b 7 6 RxCRCEn Access Rights r/w 5 4 RxSpeed dy dy 3 2 RxNoErr RxMultiple r/w r/w dy 1 0 RxFraming dy dy Table 54. Description of RxModeReg bits Bit Symbol Description 7 RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 54. 9.2.2.5 Description of RxModeReg bits Bit Symbol Description 1 to 0 RxFraming Defines the expected framing for data reception. Value Description 00 ISO/IEC 14443A/MIFARE and Passive Communication mode 106 kbit 01 Active Communication mode 10 FeliCa and Passive Communication mode 212 and 424 kbit 11 ISO/IEC 14443B TxControlReg Controls the logical behavior of the antenna driver pins Tx1 and Tx2. Table 55.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.6 TxAutoReg Controls the settings of the antenna driver. Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b 7 6 AutoRF OFF Access Rights 5 Force100 Auto ASK WakeUp r/w r/w r/w 4 3 0 CAOn RFU r/w 2 1 0 InitialRF Tx2RFAuto Tx1RFAuto On En En r/w r/w r/w Table 58.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.7 TxSelReg Selects the sources for the analog part. Table 59. Access Rights Table 60. Bit TxSelReg register (address 16h); reset value: 10h, 00010000b 7 6 0 0 RFU RFU 5 4 3 DriverSel r/w r/w 2 1 0 SigOutSel r/w r/w r/w r/w Description of TxSelReg bits Symbol Description 7 to 6 - Reserved for future use. 5 to 4 DriverSel Selects the input of driver Tx1 and Tx2.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 60. Description of TxSelReg bits …continued Bit Symbol Description 3 to 0 SigOutSel Selects the input for the SIGOUT Pin. Value Description 0000 Tristate 0001 Low 0010 High 0011 TestBus signal as defined by bit TestBusBitSel in register TestSel1Reg.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.8 RxSelReg Selects internal receiver settings. Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b 7 6 5 4 3 UartSel Access Rights 1 0 r/w r/w r/w RxWait r/w r/w Table 62. Description of RxSelReg bits Bit Symbol 7 to 6 UartSel 5 to 0 9.2.2.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.10 DemodReg Defines demodulator settings. Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b 7 6 AddIQ Access Rights Table 66. r/w 5 4 FixIQ TPrescal Even r/w r/w r/w 3 2 1 TauRcv r/w 0 TauSync r/w r/w r/w Description of DemodReg bits Bit Symbol Description 7 to 6 AddIQ Defines the use of I and Q channel during reception Note: FixIQ has to be set to logic 0 to enable the following settings.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.11 FelNFC1Reg Defines the length of the FeliCa Sync bytes and the minimum length of the received packet. Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b 7 6 5 4 FelSyncLen Access Rights Table 68. r/w r/w 3 1 0 r/w r/w DataLenMin r/w r/w r/w r/w Description of FelNFC1Reg bits Bit Symbol Description 7 to 6 FelSyncLen Defines the length of the Sync bytes.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.12 FelNFC2Reg Defines the maximum length of the received packet. Table 69. Access Rights FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b 7 6 WaitForSelected ShortTimeSlot r/w r/w 5 4 3 2 1 0 r/w r/w DataLenMax r/w r/w r/w r/w Table 70. Description of FelNFC2Reg bits Bit Symbol Description 7 WaitForSelected Set to logic 1, the AutoColl command is only terminated automatically when: 1.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.13 MifNFCReg Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating mode. Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b 7 6 5 SensMiller Access Rights r/w r/w 4 3 TauMiller r/w r/w r/w 2 1 MFHalted r/w 0 TxWait r/w r/w Table 72. Description of MifNFCReg bits Bit Symbol Description 7 to 5 SensMiller These bits define the sensitivity of the Miller decoder.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.14 ManualRCVReg Allows manual fine tuning of the internal receiver. Remark: For standard applications it is not recommended to change this register settings. Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b Access Rights 7 6 5 4 3 2 0 FastFilt MF_SO Delay MF_SO Parity Disable LargeBW PLL Manual HPCF RFU r/w r/w r/w r/w r/w 1 0 HPFC r/w r/w Table 74.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.2.15 TypeBReg Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b 7 6 5 RxSOF Req RxEOF Req 0 r/w r/w RFU Access Rights 4 3 2 EOFSOF NoTxSOF NoTxEOF Width r/w r/w r/w 1 0 TxEGT r/w r/w Table 76. Description of TypeBReg bits Bit Symbol Description 7 RxSOFReq If this bit is set to logic 1, the SOF is required. A datastream starting without SOF is ignored.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 77. SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b 7 6 5 4 3 BR_T0 Access Rights PN512 Product data sheet COMPANY PUBLIC r/w r/w 2 1 0 r/w r/w BR_T1 r/w r/w r/w r/w Table 78. Description of SerialSpeedReg bits Bit Symbol Description 7 to 5 BR_T0 Factor BR_T0 to adjust the transfer speed, for description see Section 10.3.2 “Selectable UART transfer speeds”.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.3 Page 2: Configuration 9.2.3.1 PageReg Selects the register page. Table 79. PageReg register (address 20h); reset value: 00h, 00000000b 7 6 5 4 3 2 UsePageSelect 0 0 0 0 0 r/w RFU RFU RFU RFU RFU Access Rights 1 0 PageSelect r/w r/w Table 80. Description of PageReg bits Bit Symbol 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.3.3 Table 84. Description of CRCResultReg bits Bit Symbol Description 7 to 0 CRCResultLSB This register shows the actual value of the least significant byte of the CRCResult register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. GsNOffReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off. Table 85.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.3.4 ModWidthReg Controls the modulation width settings. Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b 7 6 5 4 3 2 1 0 r/w r/w r/w ModWidth Access Rights r/w r/w r/w r/w r/w Table 88.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.3.6 RFCfgReg Configures the receiver gain and RF level detector sensitivity. Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b 7 6 5 RFLevelAmp Access Rights Product data sheet COMPANY PUBLIC 3 2 RxGain r/w r/w r/w 1 0 RFLevel r/w r/w r/w r/w Table 92. Description of RFCfgReg bits Bit Symbol Description 7 RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ amplifier.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.3.7 GsNOnReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b 7 6 5 4 3 2 CWGsNOn Access Rights r/w r/w r/w 1 0 ModGsNOn r/w r/w r/w r/w r/w Table 94.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.3.9 ModGsPReg Defines the driver P-output conductance during modulation. Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b Access Rights 7 6 5 0 0 RFU RFU 4 3 2 1 0 r/w r/w r/w ModGsP r/w r/w r/w Table 98. Description of ModGsPReg bits Bit Symbol Description 7 to 6 - Reserved for future use.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 100. Description of TModeReg bits …continued Bit Symbol Description 6 to 5 TGated The internal timer is running in gated mode. Note: In the gated mode, the bit TRunning is 1 when the timer is enabled by the register bits. This bit does not influence the gating signal.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.3.11 TReloadReg Describes the 16-bit long timer reload value. Note: The Reload value is split into two 8-bit registers. Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 r/w r/w r/w TReloadVal_Hi Access Rights r/w r/w r/w r/w r/w Table 104.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.3.12 TCounterValReg Contains the current value of the timer. Note: The Counter value is split into two 8-bit register. Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 r r r TCounterVal_Hi Access Rights r r r r r Table 108. Description of the higher TCounterValReg bits Bit Symbol Description 7 to 0 TCounterVal_Hi Current value of the timer, higher 8 bits.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 112. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.4.2 TestSel1Reg General test signal configuration. Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b Access Rights 7 6 5 - - r/w r/w 4 3 SAMClockSel r/w 2 SAMClkD1 r/w 1 0 TstBusBitSel r/w r/w r/w r/w Table 114. Description of TestSel1Reg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 4 SAMClockSel Defines the source for the 13.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.4.4 TestPinEnReg Enables the pin output driver on the 8-bit parallel bus. Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b 7 6 5 4 3 RS232LineEn Access Rights 2 1 0 r/w r/w r/w TestPinEn r/w r/w r/w r/w r/w Table 118. Description of TestPinEnReg bits Bit Symbol Description 7 RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are disabled.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.4.6 TestBusReg Shows the status of the internal testbus. Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 r r r r TestBus Access Rights r r r r Table 122. Description of TestBusReg bits 9.2.4.7 Bit Symbol Description 7 to 0 TestBus Shows the status of the internal testbus. The testbus is selected by the register TestSel2Reg. See Section 20 “Testsignals”.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 r r r r Version Access Rights r r r r Table 126. Description of VersionReg bits Bit Symbol Description 7 to 0 Version 80h indicates PN512 version 1.0, differences to version 2.0 are described within Section 21 “Errata sheet” on page 109. 82h indicates PN512 version 2.0, which covers also the industrial version.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.4.9 AnalogTestReg Controls the pins AUX1 and AUX2 Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b 7 6 5 4 3 AnalogSelAux1 Access Rights r/w r/w r/w 2 1 0 AnalogSelAux2 r/w r/w r/w r/w r/w Table 128. Description of AnalogTestReg bits Bit Symbol Description 7 to 4 AnalogSelAux1 Controls the AUX pin. 3 to 0 AnalogSelAux2 Note: All test signals are described in Section 20 “Testsignals”.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.4.10 TestDAC1Reg Defines the testvalues for TestDAC1. Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb Access Rights 7 6 5 0 0 RFT RFU 4 3 2 1 0 r/w r/w TestDAC1 r/w r/w r/w r/w Table 130. Description of TestDAC1Reg bits 9.2.4.11 Bit Symbol Description 7 - Reserved for production tests. 6 - Reserved for future use. 5 to 0 TestDAC1 Defines the testvalue for TestDAC1.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 9.2.4.13 RFTReg Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b 7 Access Rights 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 RFT RFT RFT RFT RFT RFT RFT RFT Table 136. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests. Table 137.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 141. Connection protocol for detecting different interface types Pin Interface type UART (input) I2C-bus (I/O) SPI (output) SDA RX NSS SDA I2C 0 0 1 EA 0 1 EA D7 TX MISO SCL D6 MX MOSI ADR_0 D5 DTRQ SCK ADR_1 D4 - - ADR_2 D3 - - ADR_3 D2 - - ADR_4 D1 - - ADR_5 Table 142.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 10.2 Serial Peripheral Interface A serial peripheral interface (SPI compatible) is supported to enable high-speed communication to the host. The interface can handle data speeds up to 10 Mbit/s. When communicating with a host, the PN512 acts as a slave, receiving data from the external host for register settings, sending and receiving data relevant for RF interface communication.
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PN512 NXP Semiconductors Full NFC Forum compliant solution The first send byte defines both the mode and the address byte. Table 144. MOSI and MISO byte order Line Byte 0 Byte 1 Byte 2 MOSI address 0 data 0 MISO X[1] X[1] [1] To Byte n Byte n + 1 data 1 ... data n  1 data n X[1] ... X[1] X[1] X = Do not care. Remark: The MSB must be sent first. 10.2.3 SPI address byte The address byte has to meet the following format. The MSB of the first byte defines the mode used.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 146. BR_T0 and BR_T1 settings BR_Tn Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 BR_T0 factor 1 1 2 4 8 16 32 64 BR_T1 range 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 Table 147. Selectable UART transfer speeds Transfer speed (kBd) SerialSpeedReg value Transfer speed accuracy (%)[1] Decimal Hexadecimal 7.2 250 FAh 0.25 9.6 235 EBh 0.32 14.4 218 DAh 0.25 19.2 203 CBh 0.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission. Read data: To read data using the UART interface, the flow shown in Table 149 must be used. The first byte sent defines both the mode and the address. Table 149.
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PN512 NXP Semiconductors Full NFC Forum compliant solution The MSB of the first byte sets the mode used. To read data from the PN512, the MSB is set to logic 1. To write data to the PN512 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 151. Table 151. Address byte 0 register; address MOSI 7 (MSB) 6 5 1 = read 0 = write reserved address 4 3 2 1 0 (LSB) 10.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 10.4.1 Data validity Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW. SDA SCL data line stable; data valid change of data allowed mbc621 Fig 18. Bit transfer on the I2C-bus 10.4.2 START and STOP conditions To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 10.4.4 Acknowledge An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 10.4.5 7-Bit addressing During the I2C-bus address procedure, the first byte after the START condition is used to determine which slave will be selected by the master. Several address numbers are reserved. During device configuration, the designer must ensure that collisions with these reserved addresses cannot occur. Check the I2C-bus specification for a complete list of reserved addresses.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 10.4.7 Register read access To read out data from a specific register address in the PN512, the host controller must use the following procedure: • Firstly, a write access to the specific register address must be performed as indicated in the frame that follows • The first byte of a frame indicates the device address according to the I2C-bus rules • The second byte indicates the register address.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 10.4.8 High-speed mode In High-speed mode (HS mode), the device can transfer information at data rates of up to 3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode (F/S mode) for bidirectional communication in a mixed-speed bus system. 10.4.9 High-speed transfer To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to I2C-bus operation.
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PN512 NXP Semiconductors Full NFC Forum compliant solution A 8-bit master code 0000 1xxx S t1 tH SDA high SCL high 1 2 to 5 6 7 8 9 F/S mode R/W 7-bit SLA Sr n + (8-bit data A + A/A) Sr P SDA high SCL high 1 2 to 5 6 7 8 9 1 2 to 5 6 7 8 9 If P then F/S mode HS mode If Sr (dotted lines) then HS mode tH tFS = Master current source pull-up msc618 = Resistor pull-up Fig 25.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 10.4.11 Switching between F/S mode and HS mode After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected PN512 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting. The following actions are taken: 1.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 11.2 Separated Read/Write strobe non multiplexed address ADDRESS DECODER low PN512 address bus NCS ADDRESS DECODER PN512 NCS A5* low address bus (A0...A3[A5*]) A4* low A0...A3[A5*] A3 high A2 high data bus (D0...D7) A1 high D0...D7 A0 multiplexed address/data AD0...AD7) D0...
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PN512 NXP Semiconductors Full NFC Forum compliant solution 12. Analog interface and contactless UART 12.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data. The contactless UART handles the protocol requirements for the communication protocols in cooperation with the host.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 154.
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PN512 NXP Semiconductors Full NFC Forum compliant solution The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel in register RFCfgReg. The sensitivity itself depends on the antenna configuration and tuning. Possible sensitivity levels at the RX pin are listed in the Table 154. Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated) V~Rx [Vpp] RFLevel ~2 1111 ~1.4 1110 ~0.99 1101 ~0.69 1100 ~0.49 1011 ~0.35 1010 ~0.
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PN512 NXP Semiconductors Full NFC Forum compliant solution HOST INTERFACES REGISTERS REGISTERSETTING FOR THE DETECTED MODE NFC @ 106 kbit/s NFC @ 212 kbit/s NFC @ 424 kbit/s DATA MODE DETECTOR RECEIVER I/Q DEMODULATOR PN512 RX 001aan225 Fig 28. Data mode detector PN512 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.6 — 2 December 2014 111346 © NXP Semiconductors N.V. 2014. All rights reserved.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 12.5 Serial data switch Two main blocks are implemented in the PN512. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins SIGIN and SIGOUT.
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PN512 NXP Semiconductors Full NFC Forum compliant solution HOST CONTROLLER PN512 SPI, I2C, SERIAL UART 1. secure access module (SAM) mode FIFO AND STATE MACHINE SIGOUT SERIAL SIGNAL SWITCH SIGIN SECURE CORE IC CONTACTLESS UART 2. contactless card mode 001aan226 Fig 30. Communication flows using the S2C interface Configured in the Secure Access Mode the host controller can directly communicate to the Secure IC via SIGIN/SIGOUT.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 12.6.1 Signal shape for Felica S2C interface support The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN. The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized demodulated signal. The clock and the demodulated signal is combined by using the logical function exclusive or. To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and SIGIN. The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of the Contactless Card mode or internally generated in terms of Secure Access mode.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 12.7 Hardware support for FeliCa and NFC polling 12.7.1 Polling sequence functionality for initiator 1. Timer: The PN512 has a timer, which can be programmed in a way that it generates an interrupt at the end of each timeslot, or if required an interrupt is generated at the end of the last timeslot. 2. The receiver can be configured in a way to receive continuously. In this mode it can receive any number of packets.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 12.7.3 Additional hardware support for FeliCa and NFC Additionally to the polling sequence support for the Felica mode, the PN512 supports the check of the Len-byte. The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg: DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet length. This register is six bit long. Each bit represents a length of four bytes.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 13. FIFO buffer An 8  64 bit FIFO buffer is used in the PN512. It buffers the input and output data stream between the host and the PN512’s internal state machine. This makes it possible to manage data streams up to 64 bytes long without the need to take timing constraints into account. 13.1 Accessing the FIFO buffer The FIFO buffer input and output data bus is connected to the FIFODataReg register.
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PN512 NXP Semiconductors Full NFC Forum compliant solution If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to Equation 4: LoAlert = FIFOLength  WaterLevel (4) 14. Interrupt request system The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if activated, by pin IRQ.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 15. Timer unit A timer unit is implemented in the PN512. The external host controller may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: • • • • • Time-out counter Watch-dog counter Stop watch Programmable one-shot Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time.
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PN512 NXP Semiconductors Full NFC Forum compliant solution To indicate 25 us it is required to count 339 clock cycles. This means the value for TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us. The timer can count up to 65535 timeslots of each 25 s. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. PN512 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 16. Power reduction modes 16.1 Hard power-down Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pins and clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or LOW level. 16.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 17. Oscillator circuitry PN512 OSCOUT OSCIN 27.12 MHz 001aan231 Fig 35. Quartz crystal connection The clock applied to the PN512 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore, is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible.
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PN512 NXP Semiconductors Full NFC Forum compliant solution device activation oscillator clock stable clock ready tstartup td tosc t 001aak596 Fig 36. Oscillator start-up time 19. PN512 command set The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see Table 158) to the CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 19.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 19.3 PN512 command overview Table 158.
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PN512 NXP Semiconductors Full NFC Forum compliant solution The PN512 has to be configured after each power up, before using the automatic Anticollision/Polling function (AutoColl command). During a hard power down (reset pin) this configuration remains unchanged. This command terminates automatically when finished and the active command is idle. 19.3.1.3 Generate RandomID This command generates a 10-byte random number which is initially stored in the internal buffer.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 19.3.1.8 Transceive This command continuously repeats the transmission of data from the FIFO buffer and the reception of data from the RF field. The first action is transmit and after transmission the command is changed to receive a data stream. Each transmit process must be started by setting the BitFramingReg register’s StartSend bit to logic 1. This command must be cleared by writing any command to the CommandReg register.
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PN512 NXP Semiconductors Full NFC Forum compliant solution MODE detection RXF raming 00 10 NFCIP-1 106 kB aud ISO14443-3 MFHalted = 1 J HALT REQA, WUPA, nAC, REQA, WUPA, nSELECT, HLTA, AC, error nAC, SELECT, nSELECT, error WUPA REQA, AC, nAC, SELECT, nSELECT, HLTA READY* AC NPCIP-1 > 106 kB aud FELICA N IDLE REQA, WUPA, nAC, REQA, nSELECT, HLTA, WUPA, error AC, SELECT, nSELECT, error AC nAC SELECT nSELECT HLTA MODEO polling, polling response REQA, WUPA READY SELECT SELECT ACTIVE* A
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PN512 NXP Semiconductors Full NFC Forum compliant solution MIFARE (Card Operation mode): The MIFARE anticollision is finished and the command has automatically changed to transceive. The FIFO contains the first command after the Select. The bit TargetActivated in the Status2Reg register is set to logic 1. Felica (Card Operation mode): The FeliCa polling command is finished and the command has automatically changed to transceive.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 19.3.1.11 SoftReset This command performs a reset of the device. The configuration data of the internal buffer remains unchanged. All registers are set to the reset values. This command automatically terminates when finished. Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to 9.6 kBd. PN512 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 20. Testsignals 20.1 Selftest The PN512 has the capability to perform a digital selftest. To start the selftest the following procedure has to be performed: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command. 3. Enable the Selftest by writing the value 09h to the register AutoTestReg. 4. Write 00h to the FIFO. 5. Start the Selftest with the CalcCRC Command. 6.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 161. Testsignal routing (TestSel2Reg = 0Dh) Pins Testsignal D6 D5 D4 D3 D2 D1 D0 clkstable clk27/8 clk27rf/8 clkrf13rf/4 clk27 clk27rf clk13rf Table 162. Description of Testsignals Pins Testsignal Description D6 clkstable shows if the oscillator delivers a stable signal.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 165. Testsignals description SelAux Description for Aux1 / Aux2 1101 RxActive 1110 Subcarrier detected 1111 TstBusBit Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the register AnalogTestReg. Note: The DAC has a current output, it is recommended to use a 1 k pull-down resistance at pins AUX1/AUX2. 20.4 PRBS Enables the PRBS9 or PRBS15 sequence according to ITU-TO150.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Especially when using time slot protocols, it is needed that the error flag is copied into the status information of the frame. When using the RxMultiple feature (see Section 9.2.2.4 on page 39) within version 1.0 the protocol error flag is not included in the status information for the frame. In addition the CRCOk is copied instead of the CRCErr. This can be a problem in frames without length information e.g. ISO/IEC 14443-B. The version 1.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 23. Limiting values Table 166. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDDA Min Max Unit analog supply voltage 0.5 +4.0 V VDDD digital supply voltage 0.5 +4.0 V VDD(PVDD) PVDD supply voltage 0.5 +4.0 V VDD(TVDD) TVDD supply voltage 0.5 +4.0 V VDD(SVDD) SVDD supply voltage 0.5 +4.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 167. Operating conditions …continued Symbol Parameter Conditions VDD(PVDD) PVDD supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V Min Typ Max Unit 1.6 - 3.6 V VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Ri input resistance VDDA = 3 V; receiver active; VRX(p-p) = 1 V; 1.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Pins AUX1 and AUX2 VOH HIGH-level output voltage VDDD = 3 V; IO = 4 mA VDDD  0.4 - VDDD V VOL LOW-level output voltage VDDD = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 169.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 169. Characteristics …continued Symbol Parameter Conditions Ipd power-down current VDDA = VDDD = VDD(TVDD) = VDD(PVDD) = 3 V Min Typ Max Unit hard power-down; pin NRSTPD set LOW [2] - - 15 A soft power-down; RF level detector on [2] - - 30 A Clock frequency fclk clock frequency - 27.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Vmod Vi(p-p)(max) Vi(p-p)(min) VMID 13.56 MHz carrier 0V 001aak012 Fig 39. Pin RX input voltage range 26.1 Timing characteristics Table 170.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 171. I2C-bus timing in Fast mode …continued Symbol Parameter Conditions tSU;DAT data set-up time Fast mode High-speed Unit mode Min Max Min Max 100 - 10 - ns tr rise time SCL signal 20 300 10 40 ns tf fall time SCL signal 20 300 10 40 ns tr rise time SDA and SCL signals 20 300 10 80 ns tf fall time SDA and SCL signals 20 300 10 80 ns tBUF bus free time between a STOP and START condition 1.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 26.2 8-bit parallel interface timing 26.2.1 AC symbols Each timing symbol has five characters. The first character is always 't' for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position): Table 172.
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PN512 NXP Semiconductors Full NFC Forum compliant solution tLHLL ALE tWHCH tCLWL NCS tLLWL tWHWL tWLWH tWHWL NWR NRD tAVLL tWLDV tLLAX tWHDX tRHDZ tRLDV D0...D7 D0...D7 multiplexed addressbus A0...A3 tWHAX tAVWL SEPARATED ADDRESSBUS A0...A3 A0...A3 001aan233 Fig 42. Timing diagram for separated Read/Write strobe Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care.
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PN512 NXP Semiconductors Full NFC Forum compliant solution tLHLL ALE tSHCH tCLSL NCS tRVSL tSHRX R/NW tLLSL tSHSL tSLSH tSHSL NDS tAVLL tSLDV, R tSLDV, W tLLAX D0...D7 D0...D7 multiplexed addressbus A0...A3 A0...A3 tSHDX tSHDZ tSHAX tAVSL SEPARATED ADDRESSBUS A0...A3 001aan234 Fig 43. Timing diagram for common Read/Write strobe Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 27. Package information The PN512 can be delivered in 3 different packages. Table 175. Package information PN512 Product data sheet COMPANY PUBLIC Package Remarks HVQFN32 8-bit parallel interface not supported HVQFN40 Supports the 8-bit parallel interface TFBGA64 Ball grid array facilitating development of an PCI compliant device All information provided in this document is subject to legal disclaimers. Rev. 4.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 28. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-1 terminal 1 index area A A1 E c detail X C e1 e 1/2 e b 9 y y1 C v M C A B w M C 16 L 17 8 e e2 Eh 1/2 1 terminal 1 index area e 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
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PN512 NXP Semiconductors Full NFC Forum compliant solution HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A B D SOT618-1 terminal 1 index area A A1 E c detail X e1 e C v w 1/2 e b 11 20 C A B C y y1 C L 21 10 e Eh e2 1/2 e 1 30 terminal 1 index area 40 31 X Dh 0 2.5 Dimensions (mm are the original dimensions) Unit mm A(1) A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.
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PN512 NXP Semiconductors Full NFC Forum compliant solution SOT1336-1 TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls A B D ball A1 index area A A2 E A1 detail X e1 C 1/2 e e Øv Øw b C A B C y1 C y H G e F E e2 D C 1/2 e B A 1 ball A1 index area 2 3 4 5 6 7 8 X 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 A2 b max 1.15 0.35 0.80 0.45 nom 1.00 0.30 0.70 0.40 min 0.90 0.25 0.65 0.35 D E e 5.6 5.5 5.4 5.6 5.5 5.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 29. Abbreviations Table 176.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 32. Revision history Table 177. Revision history Document ID Release date Data sheet status Change notice Supersedes PN512 v.4.6 20141202 Product data sheet - PN512 v.4.5 Modifications: PN512 v.4.5 Modifications: PN512 v.4.4 Modifications: PN512 v.4.3 Modifications: PN512 v.4.2 Modifications: PN512 v.4.1 Modifications: PN512 v.4.0 Modifications: PN512 v.3.9 Modifications: PN512 v.3.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 33. Legal information 33.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
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PN512 NXP Semiconductors Full NFC Forum compliant solution 35. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Quick reference data . . . . . . . . . . . . . . . . . .
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PN512 NXP Semiconductors Full NFC Forum compliant solution value: EBh, 11101011b . . . . . . . . . . . . . . . . . . .51 Table 78. Description of SerialSpeedReg bits . . . . . . . . .51 Table 79. PageReg register (address 20h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .52 Table 80. Description of PageReg bits . . . . . . . . . . . . . . .52 Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52 Table 82.
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PN512 NXP Semiconductors Full NFC Forum compliant solution Table 156. CRC coprocessor parameters . . . . . . . . . . . .93 Table 157. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .95 Table 158. Command overview . . . . . . . . . . . . . . . . . . .101 Table 159. Testsignal routing (TestSel2Reg = 07h) . . . . .107 Table 160. Description of Testsignals . . . . . . . . . . . . . . .107 Table 161. Testsignal routing (TestSel2Reg = 0Dh) . . . .108 Table 162. Description of Testsignals . . . .
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PN512 NXP Semiconductors Full NFC Forum compliant solution 36. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Fig 42. Fig 43. Fig 44. Fig 45. Fig 46. Simplified block diagram of the PN512 . . . . . . . . .
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PN512 NXP Semiconductors Full NFC Forum compliant solution 37. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Different available versions. . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 3 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 6 Block diagram . . . . . . .
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PN512 NXP Semiconductors Full NFC Forum compliant solution 10.3.2 Selectable UART transfer speeds . . . . . . . . . 10.3.3 UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 I2C Bus Interface . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 START and STOP conditions . . . . . . . . . . . . . 10.4.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.4 Acknowledge . . . . . . . . . . . . . . . .
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PN512 NXP Semiconductors Full NFC Forum compliant solution 34 35 36 37 Contact information. . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 130 133 134 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.