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1. Product profile

1.1 General description

NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted

Device (SMD) plastic packages.

1.2 Features and benefits

1.3 Applications

1.4 Quick reference data

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors;

R1 = 47 k, R2 = 47 k

Rev. 4 — 21 November 2011 Product data sheet

Table 1. Product overview

Type number Package PNP/PNP

complement

NPN/NPN

complement

Package

configuration

NXP JEITA

PEMD12 SOT666 - PEMB2 PEMH2 ultra small and flat

lead

PUMD12 SOT363 SC-88 PUMB2 PUMH2 very small

 100 mA output current capability  Reduces component count

 Built-in bias resistors  Reduces pick and place costs

 Simplifies circuit design  AEC-Q101 qualified

 Low current peripheral driver

 Control of IC inputs

 Replaces general-purpose transistors in digital applications

Table 2. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

CEO

collector-emitter voltage open base - - 50 V

output current - - 100 mA

R1 bias resistor 1 (input) 33 47 61 k

R2/R1 bias resistor ratio 0.8 1 1.2

Summary of content (16 pages)

PAGE 1
PEMD12; PUMD12 NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k Rev. 4 — 21 November 2011 Product data sheet 1. Product profile 1.1 General description NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted Device (SMD) plastic packages. Table 1. Product overview Type number Package NXP JEITA PNP/PNP complement NPN/NPN complement Package configuration PEMD12 SOT666 - PEMB2 PEMH2 ultra small and flat lead PUMD12 SOT363 SC-88 PUMB2 PUMH2 very small 1.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 2. Pinning information Table 3. Pinning Pin Description Simplified outline 1 GND (emitter) TR1 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 5 input (base) TR2 6 output (collector) TR1 6 5 4 Graphic symbol 6 5 R1 4 R2 TR2 1 2 3 TR1 R2 001aab555 1 R1 2 3 006aaa143 3. Ordering information Table 4.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 5. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 006aac749 400 Ptot (mW) 300 200 100 0 -75 -25 25 75 125 175 Tamb (°C) FR4 PCB, standard footprint Fig 1. Per device: Power derating curve for SOT363 (SC-88) and SOT666 6. Thermal characteristics Table 7.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 006aac751 103 duty cycle = 1 Zth(j-a) (K/W) 0.75 0.5 0.33 0.2 102 0.1 0.05 0.02 10 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) FR4 PCB, standard footprint Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration for PEMD12 (SOT666); typical values 006aac750 103 duty cycle = 1 Zth(j-a) (K/W) 0.75 0.5 0.33 0.2 102 0.1 0.05 0.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 7. Characteristics Table 8. Characteristics Tamb = 25 C unless otherwise specified.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 006aac752 103 hFE 006aac753 1 (1) VCEsat (V) (2) (3) 102 (1) (2) 10-1 (3) 10 1 10-1 1 102 10 10-2 10-1 1 IC (mA) VCE = 5 V IC/IB = 20 (1) Tamb = 100 C (1) Tamb = 100 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 40 C (3) Tamb = 40 C Fig 4. TR1 (NPN): DC current gain as a function of collector current; typical values Fig 5.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 006aac756 2.0 006aac757 103 Cc (pF) 1.6 fT (MHz) 1.2 102 0.8 0.4 10 10-1 0.0 0 10 20 30 40 50 VCB (V) 102 10 IC (mA) f = 1 MHz; Tamb = 25 C Fig 8. 1 VCE = 5 V; Tamb = 25 C TR1 (NPN): Collector capacitance as a function of collector-base voltage; typical values 006aac758 103 hFE Fig 9.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 006aac760 -10 VI(on) (V) 006aac761 -10 VI(off) (V) (1) (2) (1) (3) (2) (3) -1 -1 -10-1 -10-1 -1 -102 -10 -10-1 -10-1 -1 IC (mA) -10 IC (mA) VCE = 0.3 V VCE = 5 V (1) Tamb = 40 C (1) Tamb = 40 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 100 C (3) Tamb = 100 C Fig 12.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline 1.7 1.5 6 2.2 1.8 0.6 0.5 5 6 4 1.1 0.8 5 4 2 3 0.45 0.15 0.3 0.1 1.7 1.5 2.2 1.35 2.0 1.15 1.3 1.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 11. Soldering 2.75 2.45 2.1 1.6 solder lands 0.4 (6×) 0.25 (2×) 0.538 2 1.7 1.075 0.3 (2×) 0.55 (2×) placement area solder paste occupied area 0.325 0.375 (4×) (4×) Dimensions in mm 1.7 0.45 (4×) 0.6 (2×) 0.5 (4×) 0.65 (2×) sot666_fr Reflow soldering is the only recommended soldering method. Fig 18.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 2.65 solder lands 2.35 1.5 0.4 (2×) 0.6 0.5 (4×) (4×) solder resist solder paste 0.5 (4×) 0.6 (2×) occupied area 0.6 (4×) Dimensions in mm 1.8 sot363_fr Fig 19. Reflow soldering footprint PUMD12 (SOT363) 1.5 solder lands 0.3 2.5 4.5 solder resist occupied area 1.5 Dimensions in mm 1.3 1.3 preferred transport direction during soldering 2.45 5.3 sot363_fw Fig 20.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 12. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes PEMD12_PUMD12 v.4 20111121 Product data sheet - PEMD12_PUMD12 v.3 Modifications: • The format of this document has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • • • Legal texts have been adapted to the new company name where appropriate.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14.
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PEMD12; PUMD12 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . .