SC16C754B 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 04 — 6 October 2008 Product data sheet 1. General description The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C754B offers enhanced features.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs n Software (Xon/Xoff)/hardware (RTS/CTS) flow control u Programmable Xon/Xoff characters u Programmable auto-RTS and auto-CTS n Optional data flow resume by Xon any character n DMA signalling capability for both received and transmitted data n Supports 5 V, 3.3 V and 2.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 4.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 5.
SC16C754B NXP Semiconductors 61 n.c. 62 n.c. 63 CDD 64 RID 65 RXD 66 VCC 67 INTSEL 68 D0 69 D1 70 D2 71 D3 72 D4 73 D5 74 D6 75 D7 76 GND 77 RXA 78 RIA 79 CDA 80 n.c. 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs n.c. 1 60 n.c. n.c.
SC16C754B NXP Semiconductors D3 1 61 CDD D4 2 62 RID D5 3 63 RXD D6 4 64 VCC D7 5 65 INTSEL GND 6 66 D0 RXA 7 67 D1 RIA 8 68 D2 CDA 9 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs DSRA 10 60 DSRD CTSA 11 59 CTSD DTRA 12 58 DTRD VCC 13 57 GND RTSA 14 56 RTSD INTA 15 55 INTD CSA 16 54 CSD TXA 17 53 TXD SC16C754BIA68 IOW 18 52 IOR TXB 19 51 TXC CSB 20 50 CSC INTB 21 49 INTC RTSB 22 48 RTSC GND 23 47 VCC Fig 4.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2. Pin description …continued Symbol Pin Type Description I Chip Select (active LOW). These pins enable data transfers between the user CPU and the SC16C754B for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a logic LOW on the respective CSA through CSD pins. I Clear to Send (active LOW).
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2. Pin description …continued Symbol Pin Type Description LQFP64 LQFP80 PLCC68 IOW 9 11 18 I Input/Output Write strobe (active LOW). A LOW-to-HIGH transition on IOW will transfer the contents of the data bus (D[7:0]) from the external CPU to an internal register that is defined by address bits A[2:0] and CSA and CSD. n.c.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2. Pin description …continued Symbol Pin Type Description LQFP64 LQFP80 PLCC68 VCC 4, 21, 35, 52 6, 46, 66 13, 47, 64 I Power supply input. XTAL1 25 31 35 I Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 14).
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.2 Hardware flow control Hardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled/disabled independently by programming EFR[7:6]. With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and de-activates the RTS output when the RX FIFO is sufficiently full.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.2.1 Auto-RTS Auto-RTS data flow control originates in the receiver block (see Figure 1 “Block diagram of SC16C754B”). Figure 6 shows RTS functional timing. The receiver FIFO trigger levels used in auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is de-asserted.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.3 Software flow control Software flow control is enabled through the enhanced feature register and the modem control register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 3 shows software flow control options. Table 3.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.3.2 TX Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the halt trigger level programmed in TCR[3:0]. Xon1/Xon2 character is transmitted when the RX FIFO reaches the resume trigger level programmed in TCR[7:4]. The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the FIFO.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RX FIFO, but assumes the interrupt latency is fairly long. UART1 will continue sending characters until a total of 60 characters have been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt transmission.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.5 Interrupts The SC16C754B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 7:5 and 3:0.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.5.1 Interrupt mode operation In interrupt mode (if any bit of IER[3:0] is ‘1’) the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 9 shows interrupt mode operation.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.6 DMA operation There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time. 6.6.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.6.2 Block DMA transfers (DMA mode 1) Figure 12 shows TXRDY and RXRDY in DMA mode 1. wrptr TX trigger level TXRDY RX RXRDY rdptr FIFO full trigger level wrptr TXRDY RXRDY rdptr FIFO EMPTY 002aaa869 Fig 12. TXRDY and RXRDY in DMA mode 1 6.6.2.1 Transmitter TXRDY is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full. 6.6.2.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.8 Break and time-out conditions An RX idle condition is detected when the receiver line, RX, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6]. 6.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 7. Baud rates using a 1.8432 MHz crystal Desired baud rate Divisor used to generate 16× clock 50 2304 75 1536 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 Table 8. 0.69 2.86 Baud rates using a 3.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs XTAL1 XTAL2 XTAL1 X1 1.8432 MHz C1 22 pF XTAL2 X1 1.8432 MHz C2 33 pF C1 22 pF 1.5 kΩ C2 47 pF 002aaa870 Fig 14. Crystal oscillator connection 7. Register descriptions Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 9. Table 9.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 10 lists and describes the SC16C754B internal registers. Table 10.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Remark: Refer to the notes under Table 9 for more register access information. 7.1 Receiver Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.3 FIFO Control Register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11 shows FIFO control register bit settings. Table 11. FIFO control register bits description Bit Symbol Description 7:6 FCR[7] (MSB), RX trigger. Sets the trigger level for the RX FIFO.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12 shows the line control register bit settings. Table 12. Line control register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.5 Line Status Register (LSR) Table 13 shows the line status register bit settings. Table 13. Line status register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.6 Modem Control Register (MCR) The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 14 shows modem control register bit settings. Table 14. Modem control register bits description Bit Symbol Description 7 MCR[7][1] Clock select. logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6][1] TCR and TLR enable.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 15 shows modem status register bit settings per channel. Table 15.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW to HIGH. The INT output signal is activated in response to interrupt generation. Table 16 shows the interrupt enable register bit settings. Table 16.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17 shows interrupt identification register bit settings. Table 17. Interrupt identification register bits description Bit Symbol Description 7:6 IIR[7:6] Mirror the contents of FCR[0]. 5 IIR[5] RTS/CTS LOW-to-HIGH change of state.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.10 Enhanced Feature Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. Table 19 shows the enhanced feature register bit settings. Table 19. Enhanced feature register bits description Bit Symbol Description 7 EFR[7] CTS flow control enable. logic 0 = CTS flow control is disabled (normal default condition) logic 1 = CTS flow control is enabled.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.12 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. Table 20 shows transmission control register bit settings. Table 20. Transmission control register bits description Bit Symbol Description 7:4 TCR[7:4] RX FIFO trigger level to resume transmission [(0 to 60) bytes].
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs The FIFO ready register is a read-only register that can be accessed when any of the four UARTs is selected CSA to CSD = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loopback is disabled. The address is 111. 8. Programmer’s guide The base set of registers that is used during high-speed data transfer have a straightforward access method.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 23.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 9. Limiting values Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VCC supply voltage Vn voltage on any other pin Tamb ambient temperature Tstg storage temperature Max Unit - 7 V at D7 to D0 GND − 0.3 VCC + 0.3 V at any input only pin GND − 0.3 5.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 10. Static characteristics Table 25. Static characteristics Tolerance of VCC ± 10 %, unless otherwise specified. Symbol Parameter VCC supply voltage VI input voltage Conditions VCC = 2.5 V VCC = 3.3 V and 5 V Max Min Min Typ VCC − 10 % VCC 0 - VCC 0 - VCC V 1.6 - VCC 2.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 11. Dynamic characteristics Table 26. Dynamic characteristics Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %, unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V VCC = 3.3 V VCC = 5.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs [1] Applies to external clock, crystal oscillator max 24 MHz. [2] Maximum frequency = --------------- [3] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. [4] RESET pulse must happen when CS, IOW, IOR signals are inactive. 1 t w ( clk ) 11.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs active IOW t17d RTS DTR change of state change of state CD CTS DSR change of state t18d INT change of state t18d active active active t19d active IOR active active t18d change of state RI 002aaa352 Fig 17. Modem input/output timing tWL tWH external clock tw(clk) 002aac357 1 f XTAL = --------------t w ( clk ) Fig 18. External clock timing SC16C754B_4 Product data sheet © NXP B.V.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits t20d 7 data bits active INT t21d active IOR 16 baud rate clock 002aaa113 Fig 19. Receive timing start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 t25d active data ready RXRDY t26d active IOR 002aab063 Fig 20.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit D0 RX parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit D7 first byte that reaches the trigger level t25d active data ready RXRDY t26d active IOR 002aab064 Fig 21.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit D0 TX IOW parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 active t28d D0 to D7 byte #1 t27d TXRDY active transmitter ready transmitter not ready 002aab062 Fig 23.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 12. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm SOT414-1 c y X 48 A 33 49 32 ZE e A A2 E HE (A 3) A1 wM θ bp pin 1 index Lp L 64 17 1 detail X 16 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.15 0.05 1.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 80 21 1 detail X 20 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 eD eE y X 60 A 44 43 Z E 61 bp b1 w M 68 1 E HE pin 1 index A e A4 A1 (A 3) β 9 Lp 27 k detail X 10 26 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 UNIT A D(1) E(1) e A3 eD eE HD bp b1 max. min. 4.57 4.19 mm inches 0.81 0.66 HE k 23.62 23.62 25.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 13.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 29.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 15. Revision history Table 30. Revision history Document ID Release date Data sheet status Change notice Supersedes SC16C754B_4 20081006 Product data sheet - SC16C754B_3 Modifications: • • Section 2 “Features”, 5th bullet item re-written; added Footnote 1 on page 1 Table 24 “Limiting values”: – deleted symbol VI – deleted symbol VO – added symbol Vn • Section 7.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
SC16C754B NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.1.2 6.6.2 6.6.2.1 6.6.2.2 6.7 6.8 6.9 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . .