Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsSC16C850IBS/Q900,5

1. General description

The SC16C850 is a 2.5 V to 3.3 V, low power, single channel Universal Asynchronous

Receiver and Transmitter (UART) used for serial data communications. Its principal

function is to convert parallel data into serial data and vice versa. The UART can handle

serial data rates up to 5 Mbit/s. The SC16C850 is functionally (software) compatible with

the SC16C650B. SC16C850 can be programmed to operate in extended mode (see

Section 6.2

) where additional advanced UART features are available. The SC16C850

UART provides enhanced UART functions with 128-byte FIFOs, modem control interface,

and IrDA encoder/decoder. On-board status registers provide the user with error

indications and operational status. System interrupts and modem control features may be

tailored by software to meet specific user requirements. An internal loopback capability

allows on-board diagnostics.

The SC16C850IBS with Intel (16 mode) or Motorola (68 mode) bus host interface

operates at 2.5 V to 3.3 V and is available in a very small (Micro-UART) HVQFN32

package.

The SC16C850IET with Intel (16 mode) bus host interface operates at 2.5 V to 3.3 V and

is available in a very small TFBGA36 package.

2. Features and benefits

 Single channel high performance UART

 Intel or Motorola bus interface selectable using 16/68

 2.5 V to 3.3 V operation

 Up to 5 Mbit/s data rate

 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

 128-byte receive FIFO with error flags to reduce the bandwidth requirement of the

external CPU

 128 programmable Receive and Transmit FIFO interrupt trigger levels

 128 Receive and Transmit FIFO reporting levels (level counters)

 Automatic software (Xon/Xoff) and hardware (RTS

/CTS or DTR/DSR) flow control

 Industrial temperature range (−40 °C to +85 °C)

 128 hardware and software trigger levels

 Automatic 9-bit mode (RS-485) address detection

 Automatic RS-485 driver turn-around with programmable delay

 UART software reset

 High resolution clock prescaler, from 0 to 15 with granularity of

⁄

to allow

non-standard UART clock to be used

SC16C850

2.5 V to 3.3 V UART, 5 Mbit/s (max.) with 128-byte FIFOs,

infrared (IrDA), and 16 mode or 68 mode parallel bus interface

Rev. 2 — 11 November 2010 Product data sheet

Summary of content (55 pages)

PAGE 1
SC16C850 2.5 V to 3.3 V UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface Rev. 2 — 11 November 2010 Product data sheet 1. General description The SC16C850 is a 2.5 V to 3.3 V, low power, single channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Programmable Xon/Xoff characters Software selectable baud rate generator Support IrDA version 1.0 (up to 115.2 kbit/s) Standard modem interface or infrared IrDA encoder/decoder interface Enhanced Sleep mode and low power feature Modem control functions (CTS, RTS, DSR, DTR, RI, CD) Independent transmitter and receiver enable/disable Pb-free, RoHS compliant package offered 3.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 4.
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SC16C850 NXP Semiconductors 2.5 to 3.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 5. Pinning information 5.1 Pinning SC16C850IET ball A1 index area 1 2 3 4 5 6 A B C D E F 002aad022 Transparent top view Fig 3. Pin configuration for TFBGA36 1 2 3 4 5 6 A VDD n.c. IOR n.c. XTAL2 XTAL1 B A2 n.c. n.c. IOW LOWPWR CS C A0 VSS A1 VSS TX RX D INT RTS CTS VDD D7 D6 E DTR n.c. CD D1 D3 D5 F RESET DSR RI D0 D2 D4 002aad023 Transparent top view.
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SC16C850 NXP Semiconductors 25 DSR 26 CD 27 RI 28 VDD 29 D0 D4 1 24 CTS D4 1 24 CTS 16 2 23 RESET 68 2 23 RESET D5 3 22 DTR D5 3 D6 4 21 RTS D6 4 D7 5 20 INT D7 5 RX 6 19 A0 RX 6 19 A0 TX 7 18 A1 TX 7 18 A1 CS 8 17 A2 CS 8 17 A2 20 IRQ n.c. 16 n.c. 15 VDD 14 VSS 13 R/W 12 XTAL2 11 9 002aad024 21 RTS (68 mode) XTAL1 10 n.c. 16 n.c.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 2. Symbol Pin description …continued Pin Type Description 29 I/O 30 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 2. Symbol Pin description …continued Pin Type Description 21 O Request to Send (active LOW). A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1. C6 6 I UART receive data.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 6. Functional description The SC16C850 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 4. Serial port selection (Motorola interface) H = HIGH; L = LOW. Chip Select Function CS = H none CS = L UART select 6.2 Extended mode (128-byte FIFO) The device is in the extended mode when any of these four registers contains any value other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL. 6.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 5.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 6.5 Hardware flow control When automatic hardware flow control is enabled, the SC16C850 monitors the CTS pin for a remote buffer overflow indication and controls the RTS pin for local buffer overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to a logic 1.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions (see Table 24).
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder each time the Receive Holding Register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times. 6.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 7 shows the selectable baud rate table available when using a 1.8432 MHz external clock input when MCR[7] = 0, and CLKPRES = 0x00. XTAL1 XTAL2 XTAL1 X1 1.8432 MHz XTAL2 X1 1.8432 MHz C1 22 pF C2 33 pF C1 22 pF 1.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 7. Baud rate generator programming table using a 1.8432 MHz clock when MCR[7] = 0 and CLKPRES[3:0] = 0 …continued Output baud rate (bit/s) Output 16× clock divisor (decimal) Output 16× clock divisor (hexadecimal) DLM program value (hexadecimal) DLL program value (hexadecimal) 38.4 k 3 03 00 03 57.6 k 2 02 00 02 115.2 k 1 01 00 01 6.
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SC16C850 NXP Semiconductors 2.5 to 3.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 6.11 Sleep mode Sleep mode is an enhanced feature of the SC16C850 UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] bit is set. 6.11.1 Conditions to enter Sleep mode Sleep mode is entered when: • Modem input pins are not toggling. • The serial data input line, RX, is idle for 4 character time (logic HIGH) and AFCR1[4] is logic 0.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 6.13 RS-485 features 6.13.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR[1], or if hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. AFCR2[4] will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTS pin.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 6.13.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the address byte) the receiver will try to detect an address byte that matches the programmed character in the Xoff2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the Xoff2 register, the receiver will discard these data.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the transmit FIFO.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 9. Interrupt Enable Register bits description …continued Bit Symbol Description 1 IER[1] Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO modes, this interrupt will be issued whenever the FIFO is empty.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO trigger levels. 7.3.1 FIFO mode Table 10. FIFO Control Register bits description Bit Symbol Description 7:6 FCR[7:6] Receive trigger level in 32-byte FIFO mode[1]. These bits are used to set the trigger levels for receive FIFO interrupt and flow control.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 12. TX FIFO trigger levels FCR[5] FCR[4] TX FIFO trigger level (bytes) in 32-byte FIFO mode[1] 0 0 16 0 1 8 1 0 24 1 1 30 [1] When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”). 7.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 14. Interrupt Status Register bits description …continued Bit Symbol Description 0 ISR[0] INT status. logic 0 = an interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition) 7.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 18. LCR[1:0] word length LCR[1] LCR[0] Word length (bits) 0 0 5 0 1 6 1 0 7 1 1 8 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C850 and the CPU. Table 20. Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 7.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C850 is connected. Four bits of this register are used to indicate the changed information.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: ‘first extra feature register set’, ‘second extra feature register set’, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). Table 22.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 7.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers. Table 23.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Software flow control functions[1] Table 24.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder [1] For 32-byte FIFO mode, refer to Section 7.3. 7.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. Table 27 shows the FLWCNTH register bit settings; see Section 6.5. Table 27.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 7.20 RS-485 Turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode RTS or DTR pin is used to control the direction of the line driver, after the last bit of data has been shifted out of the transmit shift register the UART will count down the value in this register.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 7.22 Advanced Feature Control Register 1 (AFCR1) Table 32. Advanced Feature Control Register 1 register bits description Bit Symbol Description 7:5 AFCR1[7:5] reserved 4 AFCR1[4] Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive. logic 0 = RX input is level-sensitive. If RX pin is LOW, the UART will not go to sleep. Once the UART is in Sleep mode, it will wake up if RX pin goes LOW.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 7.23 SC16C850 external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 33. Table 33.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 8. Limiting values Table 35. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Vn voltage on any other pin Tamb ambient temperature Tstg Ptot/pack Conditions Min Max Unit - 7 V VSS − 0.3 VDD + 0.3 V −40 +85 °C storage temperature −65 +150 °C total power dissipation per package - 500 mW operating in free air 9.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 10. Dynamic characteristics Table 37. Dynamic characteristics - Intel or 16 mode Tamb = −40 °C to +85 °C; tolerance of VDD ± 10 %; unless otherwise specified. Symbol Parameter Conditions VDD = 2.5 V VDD = 3.3 V Min Max Min Max Unit tWH pulse width HIGH 6 - 6 - ns tWL pulse width LOW 6 - 6 - ns tw(clk) clock pulse width 12.5 - 12.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Table 38. Dynamic characteristics - Motorola or 68 mode Tamb = −40 °C to +85 °C; tolerance of VDD ± 10 %; unless otherwise specified. Symbol Parameter Conditions VDD = 2.5 V Min Max Min Max tWH pulse width HIGH 6 - 6 - ns tWL pulse width LOW 6 - 6 - ns tw(clk) clock pulse width 12.5 - 12.5 - ns [1][2] VDD = 3.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 10.1 Timing diagrams th(A) valid address A0 to A2 tsu(A) th(IOW-CS) active CS td(CSL-IOWL) tw(IOW) IOW td(IOW) active th(IOWH-D) tsu(D-IOWH) D0 to D7 data 002aac690 Fig 10. General write timing (16 mode) A0 to A4 tsu(A) th(A) tw(CS) CS tsu(RWL-CSL) td(RW) th(CS-RWH) R/W tsu(D-CSH) th(CSH-D) D0 to D7 002aac408 Fig 11.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder th(A) valid address A0 to A2 tsu(A) th(IOR-CS) active CS td(CS-IOR) tw(IOR) IOR td(IOR) active td(IOR-Q) tdis(IOR-QZ) D0 to D7 data 002aac691 Fig 12. General read timing (16 mode) th(A) A0 to A4 tsu(A) tw(CS) td(CS) CS tsu(RWH-CSL) tdis(CS-QZ) R/W td(CS-Q) D0 to D7 002aac407 Fig 13.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder active IOW td(IOW-Q) RTS DTR change of state change of state CD CTS DSR change of state change of state td(modem-INT) INT td(modem-INT) active active active td(IOR-INTL) active IOR active active td(modem-INT) change of state RI 002aac409 Fig 15.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits td(stop-INT) 7 data bits INT(1)(2) active td(IOR-INTL) active IOR 16 baud rate clock 002aac410 (1) INT is active when RX FIFO fills up to trigger level or a time-out condition happens (see Section 6.8). (2) INT is cleared when RX FIFO drops below trigger level. Fig 17.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder start bit TX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits 7 data bits INT(1)(2) active transmitter ready td(start-INT) td(IOW-TX) IOW td(IOW-INTL) active active 16 baud rate clock 002aac413 (1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder UART frame start data bits 0 TX data 1 0 1 0 stop 0 1 1 0 1 IrDA TX data 1/ bit time 2 bit time 3/ bit time 16 002aaa212 Fig 21. Infrared transmit timing IrDA RX data bit time RX data 0 to 1 16× clock delay 0 1 0 1 start 0 0 data bits 1 1 0 1 stop UART frame 002aaa213 Fig 22.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 11. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-1 terminal 1 index area A A1 E c detail X C e1 e 1/2 e b 9 y y1 C v M C A B w M C 16 L 17 8 e e2 Eh 1/2 1 terminal 1 index area e 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm B D SOT912-1 A ball A1 index area E A A2 A1 detail X e1 1/2 e e v w b F M M C C A B C y1 C y e E D e2 C B 1/2 e A ball A1 index area 1 2 3 4 5 6 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.15 0.25 0.15 0.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 12.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 41.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 14. Revision history Table 42. Revision history Document ID Release date Data sheet status Change notice Supersedes SC16C850 v.2 20101111 Product data sheet - SC16C850 v.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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SC16C850 NXP Semiconductors 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . .