Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsSC16IS750IPW,128

1. General description

The SC16IS740/750/760 is a slave I

C-bus/SPI interface to a single-channel high

performance UART. It offers data rates up to 5 Mbit/s and guarantees low operating and

sleeping current. The SC16IS750 and SC16IS760 also provide the application with 8

additional programmable I/O pins. The device comes in very small HVQFN24, TSSOP24

(SC16IS750/760) and TSSOP16 (SC16IS740) packages, which makes it ideally suitable

for handheld, battery operated applications. This family of products enables seamless

protocol conversion from I

C-bus or SPI to and RS-232/RS-485 and are fully bidirectional.

The SC16IS760 differs from the SC16IS750 in that it supports SPI clock speeds up to

15 Mbit/s instead of the 4 Mbit/s supported by the SC16IS750, and in that it supports

IrDA SIR up to 1.152 Mbit/s. In all other aspects, the SC16IS760 is functionally and

electrically the same as the SC16IS750. The SC16IS740 is functionally and electrically

identical to the SC16IS750, with the exception of the programmable I/O pins which are

only present on the SC16IS750.

The SC16IS740/750/760’s internal register set is backward-compatible with the widely

used and widely popular 16C450. This allows the software to be easily written or ported

from another platform.

The SC16IS740/750/760 also provides additional advanced features such as auto

hardware and software flow control, automatic RS-485 support, and software reset. This

allows the software to reset the UART at any moment, independent of the hardware reset

signal.

2. Features and benefits

2.1 General features

 Single full-duplex UART

 Selectable I

C-bus or SPI interface

 3.3 V or 2.5 V operation

 Industrial temperature range: 40 C to +95 C

 64 bytes FIFO (transmitter and receiver)

 Fully compatible with industrial standard 16C450 and equivalent

 Baud rates up to 5 Mbit/s in 16 clock mode

 Auto hardware flow control using RTS

/CTS

 Auto software flow control with programmable Xon/Xoff characters

 Single or double Xon/Xoff characters

 Automatic RS-485 support (automatic slave address detection)

SC16IS740/750/760

Single UART with I

C-bus/SPI interface, 64 bytes of transmit

and receive FIFOs, IrDA SIR built-in support

Rev. 7 — 9 June 2011 Product data sheet

Summary of content (63 pages)

PAGE 1
SC16IS740/750/760 Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 7 — 9 June 2011 Product data sheet 1. General description The SC16IS740/750/760 is a slave I2C-bus/SPI interface to a single-channel high performance UART. It offers data rates up to 5 Mbit/s and guarantees low operating and sleeping current. The SC16IS750 and SC16IS760 also provide the application with 8 additional programmable I/O pins.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR                 Up to eight programmable I/O pins (SC16IS750 and SC16IS760 only) RS-485 driver direction control via RTS signal RS-485 driver direction control inversion Built-in IrDA encoder and decoder interface SC16IS750 supports IrDA SIR with speeds up to 115.2 kbit/s SC16IS760 supports IrDA SIR with speeds up to 1.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 4. Ordering information Table 1. Ordering information Type number SC16IS740IPW Package Name Description Version TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 SC16IS740IPW/Q900[1] TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 5. Block diagram VDD SC16IS750/760 RESET SCL A0 I2C-BUS A1 TX 16C450 COMPATIBLE REGISTER SETS SDA RX RTS CTS IRQ 1 kΩ (3.3 V) 1.5 kΩ (2.5 V) 4 GPIO[3:0] VDD VDD GPIO REGISTER I2C/SPI GPIO4/DSR GPIO5/DTR GPIO6/CD GPIO7/RI XTAL1 Fig 1.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR VDD SC16IS750/760 RESET SCLK SO SPI SI TX 16C450 COMPATIBLE REGISTER SETS CS RX RTS CTS IRQ 1 kΩ (3.3 V) 1.5 kΩ (2.5 V) 4 GPIO[3:0] VDD GPIO REGISTER I2C/SPI GPIO4/DSR GPIO5/DTR GPIO6/CD GPIO7/RI XTAL1 Fig 3. XTAL2 VSS 002aab396 Block diagram of SC16IS750/760 SPI interface VDD SC16IS740 RESET SCLK 16C450 COMPATIBLE REGISTER SETS CS SO SPI SI TX RX RTS CTS IRQ 1 kΩ (3.3 V) 1.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 6. Pinning information 6.1 Pinning VDD 1 16 XTAL2 VDD 1 16 XTAL2 A0 2 15 XTAL1 CS 2 15 XTAL1 A1 3 14 RESET SI 3 14 RESET n.c. 4 13 RX SO 4 SCL 5 SCLK 5 SDA 6 11 CTS VSS 6 11 CTS IRQ 7 10 RTS IRQ 7 10 RTS I2C 8 SPI 8 SC16IS740IPW SC16IS740IPW/Q900 12 TX 9 VSS 13 RX SC16IS740IPW SC16IS740IPW/Q900 12 TX 9 002aab973 002aab974 a. I2C-bus interface Fig 5. b.
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SC16IS740/750/760 NXP Semiconductors 19 GPIO6/CD 20 GPIO7/RI 21 RTS RESET 1 18 GPIO5/DTR RESET 1 XTAL1 2 17 GPIO4/DSR XTAL1 2 XTAL2 3 16 VSS XTAL2 3 VDD 4 15 GPIO3 VDD 4 I2C 5 14 GPIO2 SPI 5 14 GPIO2 A0 6 13 GPIO1 CS 6 13 GPIO1 18 GPIO5/DTR 17 GPIO4/DSR 16 VSS 15 GPIO3 GPIO0 12 9 SCLK IRQ 11 8 002aab015 VSS 10 7 SI SC16IS750IBS SC16IS760IBS SO GPIO0 12 9 SCL IRQ 11 8 SDA 10 7 A1 n.c.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 2. Symbol Pin description …continued Pin Type Description TSSOP16 TSSOP24 HVQFN24 CS/A0 2 9 6 I SPI chip select or I2C-bus device address select A0. If SPI configuration is selected by I2C/SPI pin, this pin is the SPI chip select pin (Schmitt-trigger, active LOW). If I2C-bus configuration is selected by I2C/SPI pin, this pin along with A1 pin allows user to change the device’s base address.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR [4] HVQFN24 package die supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected to supply ground for proper device operation.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR UART 1 UART 2 SERIAL TO PARALLEL RX TX PARALLEL TO SERIAL RX FIFO TX FIFO FLOW CONTROL RTS PARALLEL TO SERIAL TX CTS RX FLOW CONTROL SERIAL TO PARALLEL TX FIFO RX FIFO CTS FLOW CONTROL RTS FLOW CONTROL 002aab656 Fig 8. Autoflow control (auto RTS and auto CTS) example 7.2.1 Auto RTS Figure 9 shows RTS functional timing.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.2.2 Auto CTS Figure 10 shows CTS functional timing. The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the middle of the last stop bit that is currently being sent. The auto CTS function reduces interrupts to the host system.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR There are two other enhanced features relating to software flow control: • Xon Any function (MCR[5]): Receiving any character will resume operation after recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO. • Special character (EFR[5]): Incoming data is compared to Xoff2.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR UART1 UART2 TRANSMIT FIFO RECEIVE FIFO data PARALLEL-TO-SERIAL SERIAL-TO-PARALLEL Xoff–Xon–Xoff SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL Xon1 WORD Xon1 WORD Xon2 WORD Xon2 WORD Xoff1 WORD Xoff1 WORD Xoff2 WORD compare programmed Xon-Xoff characters Xoff2 WORD 002aaa229 Fig 11. Example of software flow control 7.4 Reset and power-on sequence 7.4.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 4.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR voltage (V) oscillator starts stable clocks XTAL1 VIH 0V tstartup time (ms) 002aaf521 Fig 12. Start-up time 7.5 Interrupts The SC16IS740/750/760 has interrupt generation and prioritization (seven prioritized levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable each of the seven types of interrupts and the IRQ signal in response to an interrupt generation.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.5.1 Interrupt mode operation In Interrupt mode (if any bit of IER[3:0] is 1) the host is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 13 shows Interrupt mode operation.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.6 Sleep mode Sleep mode is an enhanced feature of the SC16IS740/750/760 UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • The serial data input line, RX, is idle (see Section 7.7 “Break and time-out conditions”). • The TX FIFO and TX shift register are empty. • There are no interrupts pending except THR.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.8 Programmable baud rate generator The SC16IS740/750/760 UART contains a programmable baud rate generator that takes any clock input and divides it by a divisor in the range between 1 and (216 – 1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 15. The output frequency of the baud rate generator is 16  the baud rate.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 7. Desired baud rate Divisor used to generate 16 clock Percent error difference between desired and actual 50 2304 0 75 1536 0 110 1047 0.026 134.5 857 0.058 150 768 0 300 384 0 600 192 0 1200 96 0 1800 64 0 2000 58 0.69 2400 48 0 3600 32 0 4800 24 0 7200 16 0 9600 12 0 19200 6 0 38400 3 0 56000 2 2.86 Table 8.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR XTAL1 XTAL2 1.8432 MHz C1 22 pF C2 33 pF 002aab402 Fig 16. Crystal oscillator circuit reference 8. Register descriptions The programming combinations for register selection are shown in Table 9. Table 9.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SC16IS740/750/760 internal registers …continued Register address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.1 Receive Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX pin. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR [1] FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the XTAL1 clock. 8.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12 shows the Line Control Register bit settings. Table 12.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 13. LCR[5] LCR[4] LCR[3] Parity selection X X 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 forced parity ‘1’ 1 1 1 forced parity ‘0’ Table 14. LCR[2] stop bit length LCR[2] Word length (bits) Stop bit length (bit times) 0 5, 6, 7, 8 1 1 5 112 1 6, 7, 8 2 Table 15.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.5 Line Status Register (LSR) Table 16 shows the Line Status Register bit settings. Table 16. Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.6 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 17 shows the Modem Control Register bit settings. Table 17.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the host. It also indicates when a control input from the modem changes state. Table 18 shows Modem Status Register bit settings. Table 18.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.9 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of state from LOW to HIGH. The IRQ output signal is activated in response to interrupt generation. Table 19 shows the Interrupt Enable Register bit settings. Table 19.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.10 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 20 shows Interrupt Identification Register bit settings. Table 20. Interrupt Identification Register bits description Bit Symbol Description 7:6 IIR[7:6] mirror the contents of FCR[0] 5:1 IIR[5:1] 5-bit encoded interrupt. See Table 21.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.11 Enhanced Features Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. Table 22 shows the enhanced feature register bit settings. Table 22. Enhanced Features Register bits description Bit Symbol Description 7 EFR[7] CTS flow control enable logic 0 = CTS flow control is disabled (normal default condition) logic 1 = CTS flow control is enabled.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.13 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. Table 23 shows Transmission Control Register bit settings. Table 23.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.16 Receiver FIFO Level register (RXLVL) This register is a read-only register, it reports the fill level of the receive FIFO. That is, the number of characters in the RX FIFO. Table 26. Receiver FIFO Level register bits description Bit Symbol Description 7 - not used; set to zeros 6:0 RXLVL[6:0] number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40) 8.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.20 I/O Control register (IOControl) This register is only available on the SC16IS750 and SC16IS760. Table 30. IOControl register bits description Bit Symbol Description 7:4 - reserved for future use 3 SRESET software reset A write to bit will reset the device.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.21 Extra Features Control Register (EFCR) Table 31. Extra Features Control Register bits description Bit Symbol Description 7 IRDA MODE IrDA mode 0 = IrDA SIR, 316 pulse ratio, data rate up to 115.2 kbit/s 1 = IrDA SIR, 14 pulse ratio, data rate up to 1.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 9.2 RS-485 RTS output inversion EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode. When the transmitter has data to be sent it will deasserts the RTS pin (logic 1), and when the last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0). 9.3 Auto RS-485 EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode).
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 10. I2C-bus operation The two lines of the I2C-bus are a serial data line (SDA) and a serial clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR acknowledgement signal from receiver SDA MSB SCL 0 S 1 6 7 8 0 1 2 to 7 ACK START condition 8 P ACK byte complete, interrupt within receiver STOP condition clock line held LOW while interrupt is serviced 002aab012 Fig 19.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR An address on the network is seven bits long, appearing as the most significant bits of the address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is shown in Figure 21.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR data transferred (n bytes + acknowledge) master write: S SLAVE ADDRESS START condition W write A DATA acknowledge A DATA acknowledge A P acknowledge STOP condition data transferred (n bytes + acknowledge) master read: S SLAVE ADDRESS START condition R read A DATA acknowledge A DATA acknowledge NA P not acknowledge STOP condition data transferred (n bytes + acknowledge) combin
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 10.3 Addressing Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. Table 32 shows how the SC16IS740/750/760’s address can be selected by using A1 and A0 pins.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 33 and Table 34 show the bits’ presentation at the subaddress byte for I2C-bus and SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the UART internal registers. Bit 7 is not used with the I2C-bus interface, but it is used by the SPI interface to indicate a read or a write operation.
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xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 34. Register address byte (SPI) Bit Name Function 7 R/W 1: read from UART 0: write to UART 6:3 A[3:0] UART’s internal register select 2:1 CH1, CH0 channel select: CH1 = 0, CH0 = 0 Other values are reserved and should not be used. 0 - not used 12. Limiting values Table 35. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 13. Static characteristics Table 36. Static characteristics VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C; unless otherwise specified. Symbol Parameter Conditions VDD = 2.5 V VDD = 3.3 V Unit Min Max Min Max 2.3 2.7 3.0 3.6 V - 6.0 - 6.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 36. Static characteristics …continued VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C; unless otherwise specified. Symbol I2C-bus Parameter Conditions VDD = 2.5 V VDD = 3.3 V Min Max Min Max Unit inputs SCL, CS/A0, SI/A1 VIH HIGH-level input voltage 1.6 5.5[1] 2.0 5.5[1] V VIL LOW-level input voltage - 0.6 - 0.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 14. Dynamic characteristics Table 37. I2C-bus timing specifications[1] All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C; and refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, except SDA output load = 400 pF.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR RESET tw(rst) td15 SCL 002aab437 Fig 26. SCL delay after reset protocol bit 7 MSB (A7) START condition (S) tSU;STA tLOW bit 0 LSB (R/W) bit 6 (A6) tHIGH 1/f acknowledge (A) STOP condition (P) SCL SCL tBUF tf tr tSP SDA tSU;DAT tHD;STA tVD;ACK tVD;DAT tHD;DAT tSU;STO 002aab489 Rise and fall times refer to VIL and VIH. Fig 27.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR ACK from slave SLAVE ADDRESS SDA W A A IOSTATE REG. ACK from slave A S SLAVE ADDRESS R ACK from master A A DATA P IRQ td4 td5 GPIOn 002aab257 Fig 30. GPIO pin interrupt (SC16IS750 and SC16IS760 only) RX next start bit stop bit start bit D0 D1 D2 D3 D4 D5 D6 D7 td6 IRQ 002aab258 Fig 31.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 38. fXTAL dynamic characteristics VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C Symbol Parameter tw1 clock pulse duration tw2 clock pulse duration Conditions [1][2] frequency on pin XTAL fXTAL VDD = 2.5 V [1] Applies to external clock, crystal oscillator max. 24 MHz. [2] 1 f XTAL = ------t w3 [3] 100 ppm is recommended. tw2 VDD = 3.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 40. SC16IS760 SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C and refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR CS SCLK SI R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0 td9 GPIOx 002aab438 R/W = 0; A[3:0] = IOState (0x0B); CH1 = 0; CH0 = 0 Fig 36. SPI write IOState to GPIO switch (SC16IS750 and SC16IS760 only) CS SCLK SI R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0 td10 DTR (GPIO5) 002aab439 R/W = 0; A[3:0] = MCR (0x04); CH1 = 0; CH0 = 0 Fig 37.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR CS SCLK SI R/W A3 A2 A1 A0 CH1 CH0 X D7 SO D6 D5 D4 D3 D2 D1 D0 td12 IRQ 002aab441 R/W = 1; A[3:0] = MSR (0x06); CH1 = 0; CH0 = 0 Fig 39. Read MSR to clear modem INT (SC16IS750 and SC16IS760 only) CS SCLK SI R/W A3 A2 A1 A0 CH1 CH0 X D7 SO D6 D5 D4 D3 D2 D1 D0 td13 IRQ 002aab442 R/W = 1; A[3:0] = IOState (0x0B); CH1 = 0; CH0 = 0 Fig 40.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm A B D SOT616-3 terminal 1 index area A A1 E c detail X e1 C 1/2 e e 12 y y1 C v M C A B w M C b 7 L 13 6 e e2 Eh 1/2 e 1 18 terminal 1 index area 24 19 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 45. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 43.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 19. Revision history Table 44. Revision history Document ID Release date Data sheet status Change notice Supersedes SC16IS740_750_760 v.7 20110609 Product data sheet - SC16IS740_750_760 v.6 Modifications: • Table 1 “Ordering information”: – Added type number SC16IS740IPW/Q900. – Added new Table note 1.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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SC16IS740/750/760 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 22. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.6 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General features . . . . . . . . . . . . . . . . . . . . . . . .