Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsSC16IS762IPW,112

1. General description

The SC16IS752/SC16IS762 is an I

C-bus/SPI bus interface to a dual-channel high

performance UART offering data rates up to 5 Mbit/s, low operating and sleeping current;

it also provides the application with 8 additional programmable I/O pins. The device

comes in very small HVQFN32 and TSSOP28 packages, which makes it ideally suitable

for hand-held, battery-operated applications. This chip enables seamless protocol

conversion from I

C-bus/SPI to RS-232/RS-485 and is fully bidirectional.

The SC16IS762 differs from the SC16IS752 in that it supports SPI clock speeds up to

15 Mbit/s instead of the 4 Mbit/s supported by the SC16IS752, and in that it supports IrDA

SIR up to 1.152 Mbit/s. In all other aspects, the SC16IS762 is functionally and electrically

the same as the SC16IS752.

The SC16IS752/SC16IS762’s internal register set is backward compatible with the widely

used and widely popular 16C450. This allows the software to be easily written or ported

from another platform.

The SC16IS752/SC16IS762 also provides additional advanced features such as auto

hardware and software flow control, automatic RS-485 support and software reset. This

allows the software to reset the UART at any moment, independent of the hardware reset

signal.

2. Features and benefits

2.1 General features

 Dual full-duplex UART

 I

C-bus or SPI interface selectable

 3.3 V or 2.5 V operation

 Industrial temperature range: 40 C to +95 C

 64 bytes FIFO (transmitter and receiver)

 Fully compatible with industrial standard 16C450 and equivalent

 Baud rates up to 5 Mbit/s in 16 clock mode

 Auto hardware flow control using RTS

/CTS

 Auto software flow control with programmable Xon/Xoff characters

 Single or double Xon/Xoff characters

 Automatic RS-485 support (automatic slave address detection)

 Up to eight programmable I/O pins

 RS-485 driver direction control via RTS

signal

SC16IS752; SC16IS762

Dual UART with I

C-bus/SPI interface, 64 bytes of transmit

and receive FIFOs, IrDA SIR built-in support

Rev. 9 — 22 March 2012 Product data sheet

Summary of content (60 pages)

PAGE 1
SC16IS752; SC16IS762 Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 9 — 22 March 2012 Product data sheet 1. General description The SC16IS752/SC16IS762 is an I2C-bus/SPI bus interface to a dual-channel high performance UART offering data rates up to 5 Mbit/s, low operating and sleeping current; it also provides the application with 8 additional programmable I/O pins.
PAGE 2
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR               RS-485 driver direction control inversion Built-in IrDA encoder and decoder supporting IrDA SIR with speeds up to 115.2 kbit/s SC16IS762 supports IrDA SIR with speeds up to 1.
PAGE 3
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 4. Ordering information Table 1. Ordering information Type number SC16IS752IPW Package Name Description Version TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5  5  0.
PAGE 4
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 5. Block diagram VDD VSS SC16IS752/ SC16IS762 16C450 COMPATIBLE REGISTER SETS SDA SCL A0 A1 VDD TXA RXA RTSA CTSA TXB RXB RTSB CTSB I2C-BUS 1 kΩ (3.3 V) 1.5 kΩ (2.5 V) IRQ RESET VDD GPIO REGISTER I2C/SPI GPIO7/RIA GPIO6/CDA GPIO5/DTRA GPIO4/DSRA GPIO3/RIB GPIO2/CDB GPIO1/DTRB GPIO0/DSRB 002aab207 XTAL1 XTAL2 a.
PAGE 5
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 6. Pinning information 6.
PAGE 6
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 6.2 Pin description Table 2. Pin description Symbol CS/A0 Pin Type Description TSSOP28 HVQFN32 10 7 I SPI chip select or I2C-bus device address select A0. If SPI configuration is selected by I2C/SPI pin, this pin is the SPI chip select pin (Schmitt-trigger active LOW).
PAGE 7
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 2. Pin description …continued Symbol Pin Type Description TSSOP28 HVQFN32 RESET 5 2 I Hardware reset (active LOW)[3] RTSA 1 30 O UART request to send (active LOW), channel A. A logic 0 on the RTSA pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the Modem Control Register MCR[1] will set this pin to a logic 0, indicating data is available.
PAGE 8
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7. Functional description The UART will perform serial-to-I2C-bus conversion on data characters received from peripheral devices or modems, and I2C-bus-to-serial conversion on data characters transmitted by the host. The complete status of the SC16IS752/SC16IS762 UART can be read at any time during functional operation by the host.
PAGE 9
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR UART 1 UART 2 SERIAL TO PARALLEL RX TX PARALLEL TO SERIAL RX FIFO TX FIFO FLOW CONTROL RTS PARALLEL TO SERIAL TX CTS RX FLOW CONTROL SERIAL TO PARALLEL TX FIFO RX FIFO CTS FLOW CONTROL RTS FLOW CONTROL 002aab656 Fig 4. Auto flow control (Auto-RTS and Auto-CTS) example 7.2.1 Auto-RTS Figure 5 shows RTS functional timing.
PAGE 10
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.2.2 Auto-CTS Figure 6 shows CTS functional timing. The transmitter circuitry checks CTS before sending the next data character. When CTS is active, the transmitter sends the next character. To stop the transmitter from sending the following character, CTS must be de-asserted before the middle of the last stop bit that is currently being sent. The Auto-CTS function reduces interrupts to the host system.
PAGE 11
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR There are two other enhanced features relating to software flow control: • Xon Any function (MCR[5]): Receiving any character will resume operation after recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO. • Special character (EFR[5]): Incoming data is compared to Xoff2.
PAGE 12
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR UART1 UART2 TRANSMIT FIFO RECEIVE FIFO data PARALLEL-TO-SERIAL SERIAL-TO-PARALLEL Xoff–Xon–Xoff SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL Xon1 WORD Xon1 WORD Xon2 WORD Xon2 WORD Xoff1 WORD Xoff1 WORD Xoff2 WORD Fig 7.
PAGE 13
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.4 Hardware Reset, Power-On Reset (POR) and Software Reset These three reset methods are identical and will reset the internal registers as indicated in Table 4. Table 4 summarizes the state of register after reset. Table 4.
PAGE 14
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.5 Interrupts The SC16IS752/SC16IS762 has interrupt generation and prioritization (seven prioritized levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable each of the seven types of interrupts and the IRQ signal in response to an interrupt generation.
PAGE 15
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.5.1 Interrupt mode operation In Interrupt mode (if any bit of IER[3:0] is 1) the host is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 8 shows Interrupt mode operation.
PAGE 16
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.6 Sleep mode Sleep mode is an enhanced feature of the SC16IS752/SC16IS762 UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • The serial data input line, RX, is idle (see Section 7.7 “Break and time-out conditions”). • The TX FIFO and TX shift register are empty. • There are no interrupts pending except THR.
PAGE 17
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Figure 10 shows the internal prescaler and baud rate generator circuitry. PRESCALER LOGIC (DIVIDE-BY-1) XTAL1 XTAL2 INTERNAL OSCILLATOR LOGIC MCR[7] = 0 input clock PRESCALER LOGIC (DIVIDE-BY-4) reference clock BAUD RATE GENERATOR LOGIC internal baud rate clock for transmitter and receiver MCR[7] = 1 002aaa233 Fig 10.
PAGE 18
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 8. Baud rates using a 3.072 MHz crystal Desired baud rate (bit/s) Divisor used to generate 16 clock Percent error difference between desired and actual 50 2304 0 75 2560 0 110 1745 0.026 134.5 1428 0.034 150 1280 0 300 640 0 600 320 0 1200 160 0 1800 107 0.312 2000 96 0 2400 80 0 3600 53 0.628 4800 40 0 7200 27 1.
PAGE 19
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8. Register descriptions The programming combinations for register selection are shown in Table 9. Table 9.
PAGE 20
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Register address NXP Semiconductors SC16IS752_SC16IS762 Product data sheet Table 10.
PAGE 21
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Register address SC16IS752/SC16IS762 internal registers …continued Register Bit 7 Bit 6 Bit 5 Bit 4 Bi
PAGE 22
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.1 Receive Holding Register (RHR) The receiver section consists of the Receive Holding Register (RHR) and the Receive Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register.
PAGE 23
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 11. Interrupt Enable Register bits description …continued Bit Symbol Description 1 IER[1] Transmit Holding Register interrupt. logic 0 = disable the THR interrupt (normal default condition) logic 1 = enable the THR interrupt 0 IER[0] Receive Holding Register interrupt.
PAGE 24
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.5 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 13 shows Interrupt Identification Register bit settings. Table 13. Interrupt Identification Register bits description Bit Symbol Description 7:6 IIR[7:6] Mirror the contents of FCR[0]. 5:1 IIR[5:1] 5-bit encoded interrupt. See Table 14.
PAGE 25
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 15. Line Control Register bits description …continued Bit Symbol Description 5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = logic 1). logic 0 = parity is not forced (normal default condition). LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data.
PAGE 26
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.7 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 19 shows Modem Control Register bit settings. Table 19. Modem Control Register bits description Bit Symbol Description 7 MCR[7][1] Clock divisor. logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6][1] IrDA mode enable.
PAGE 27
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.8 Line Status Register (LSR) Table 20 shows the Line Status Register bit settings. Table 20. Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO.
PAGE 28
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.9 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the host. It also indicates when a control input from the modem changes state. Table 21 shows Modem Status Register bit settings per channel. Table 21.
PAGE 29
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.11 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. Table 22 shows Transmission Control Register bit settings. If TCR bits are cleared, then selectable trigger levels in FCR are used in place of TCR. Table 22.
PAGE 30
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.13 Transmitter FIFO Level register (TXLVL) This register is a read-only register. It reports the number of spaces available in the transmit FIFO. Table 24. Transmitter FIFO Level register bits description Bit Symbol Description 7 - not used; set to zeros 6:0 TXLVL[6:0] number of spaces available in TX FIFO, from 0 (0x00) to 64 (0x40) 8.
PAGE 31
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.17 I/O Interrupt Enable register (IOIntEna) This register enables the interrupt due to a change in the I/O configured as inputs. If GPIO[7:4] or GPIO[3:0] are programmed as modem pins, their interrupt generation must be enabled via IER[3]. In this case, IOIntEna will have no effect on GPIO[7:4] or GPIO[3:0]. Table 28.
PAGE 32
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.19 Extra Features Control Register (EFCR) Table 30. Extra Features Control Register bits description Bit Symbol Description 7 IRDA MODE IrDA mode. 0 = IrDA SIR, 3⁄16 pulse ratio, data rate up to 115.2 kbit/s 1 = IrDA SIR, 1⁄4 pulse ratio, data rate up to 1.152 Mbit/s[1] 6 - reserved 5 RTSINVER Invert RTS signal in RS-485 mode.
PAGE 33
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.21 Enhanced Features Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. Table 31 shows the Enhanced Features Register bit settings. Table 31. Enhanced Features Register bits description Bit Symbol Description 7 EFR[7] CTS flow control enable. logic 0 = CTS flow control is disabled (normal default condition) logic 1 = CTS flow control is enabled.
PAGE 34
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 9.3 Auto RS-485 EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of operation, a ‘master’ station transmits an address character followed by data characters for the addressed ‘slave’ stations. The slave stations examine the received data and interrupt the controller if the received character is an address character (parity bit = 1).
PAGE 35
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 10. I2C-bus operation The two lines of the I2C-bus are a serial data line (SDA) and a serial clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy.
PAGE 36
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR acknowledgement signal from receiver SDA MSB SCL 0 S 1 6 7 8 0 1 2 to 7 ACK START condition 8 P ACK byte complete, interrupt within receiver STOP condition clock line held LOW while interrupt is serviced 002aab012 Fig 14.
PAGE 37
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 10.2 Addressing and transfer formats Each device on the bus has its own unique address. Before any data is transmitted on the bus, the master transmits on the bus the address of the slave to be accessed for this transaction. A well-behaved slave with a matching address, if it exists on the network, should of course acknowledge the master's addressing.
PAGE 38
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR In a single master system, the ‘Repeated START’ mechanism may be more efficient than terminating each transfer with a STOP and starting again. In a multimaster environment, the determination of which format is more efficient could be more complicated, as when a master is using repeated STARTs occupies the bus for a long time, and thus preventing other devices from initiating transfers.
PAGE 39
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 10.3 Addressing Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. Table 32 shows how the SC16IS752/SC16IS762’s address can be selected by using A1 and A0 pins.
PAGE 40
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR S SLAVE ADDRESS W A REGISTER ADDRESS(1) A nDATA A P 002aab047 White block: host to SC16IS752/SC16IS762 Grey block: SC16IS752/SC16IS762 to host (1) See Table 33 for additional information. Fig 18. Master writes to slave The register read cycle (see Figure 19) commences in a similar manner, with the master sending a slave address with the direction bit set to WRITE with a following subaddress.
PAGE 41
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0 002aab433 R/W = 0; A[3:0] = register
PAGE 42
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 34. Register address byte (SPI) Bit Name Function 7 R/W Read/write. 1 = read from UART 0 = write to UART 6:3 A[3:0] UART’s internal register select 2:1 CH1, CH0 Channel select. 00 = channel A 01 = channel B 10 = reserved 11 = reserved 0 - not used 12. Limiting values Table 35. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
PAGE 43
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 13. Static characteristics Table 36. Static characteristics VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C; unless otherwise specified. Symbol Parameter Conditions VDD = 2.5 V VDD = 3.3 V Unit Min Max Min Max 2.3 2.7 3.0 3.6 V - 2.0 - 2.0 mA 1.6 5.5[1] 2.0 5.5[1] V - 0.6 - 0.8 V - 1 - 1 A - 3 - 3 pF 1.
PAGE 44
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 36. Static characteristics …continued VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C; unless otherwise specified. Symbol I2C-bus Parameter Conditions VDD = 2.5 V VDD = 3.3 V Min Max Min Max Unit inputs SCL, CS/A0, SI/A1 VIH HIGH-level input voltage 1.6 5.5[1] 2.0 5.5[1] V VIL LOW-level input voltage - 0.6 - 0.
PAGE 45
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 14. Dynamic characteristics Table 37. I2C-bus timing specifications[1] All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C; VIL and VIH refer to input voltage of VSS to VDD. All output load = 25 pF, except SDA output load = 400 pF.
PAGE 46
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR RESET tw(rst) td15 SCL 002aab437 Fig 21. SCL delay after reset protocol bit 7 MSB (A7) START condition (S) tSU;STA tLOW bit 0 LSB (R/W) bit 6 (A6) tHIGH 1/f acknowledge (A) STOP condition (P) SCL SCL tBUF tf tr tSP SDA tSU;DAT tHD;STA tVD;ACK tVD;DAT tHD;DAT tSU;STO 002aab489 Rise and fall times refer to VIL and VIH. Fig 22.
PAGE 47
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR ACK from slave SLAVE ADDRESS SDA W A A IOSTATE REG. ACK from slave A S SLAVE ADDRESS R ACK from master A A DATA P IRQ td4 td5 GPIOn 002aab257 Fig 25. GPIO pin interrupt RX next start bit stop bit start bit D0 D1 D2 D3 D4 D5 D6 D7 td6 IRQ 002aab258 Fig 26.
PAGE 48
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 38. fXTAL dynamic characteristics VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C. Symbol Parameter Conditions tw1 clock pulse duration HIGH level tw2 clock pulse duration LOW level fXTAL [1] [2] VDD = 2.5 V [1][2] oscillator/clock frequency VDD = 3.
PAGE 49
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 39. SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = 2.5 V  0.2 V, Tamb = 40 C to +85 C; or VDD = 3.3 V  0.3 V, Tamb = 40 C to +95 C; VIL and VIH refer to input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified. Symbol Parameter Conditions VDD = 2.
PAGE 50
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR CS SCLK SI R/W A3 A2 A1 CH1 CH0 A0 X D7 D6 D5 D4 D3 D2 D1 D0 td9 GPIOx 002aab438 R/W = 0; A[3:0] = IOState (0x0B); CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B Fig 31.
PAGE 51
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR CS SCLK SI R/W A3 A2 A1 A0 CH1 CH0 X D7 SO D6 D5 D4 D3 D2 D1 D0 td12 IRQ 002aab441 R/W = 1; A[3:0] = MSR (0x06); CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B Fig 34.
PAGE 52
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 15. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm D SOT361-1 E A X c HE y v M A Z 15 28 Q A2 (A 3) A1 pin 1 index A θ Lp 1 L 14 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.
PAGE 53
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-1 terminal 1 index area A A1 E c detail X C e1 e 1/2 e b 9 y y1 C v M C A B w M C 16 L 17 8 e e2 Eh 1/2 1 terminal 1 index area e 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
PAGE 54
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology.
PAGE 55
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.
PAGE 56
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 39. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Appendix 18.
PAGE 57
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 19. Abbreviations Table 42.
PAGE 58
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
PAGE 59
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 60
SC16IS752; SC16IS762 NXP Semiconductors Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 23. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 I2C-bus features . .