user manual

8. CONFIGURATION REGISTER
The MPA-100 is equipped with an onboard register used for configuring information
such as DMA enables, DMA sources, interrupt enables, and interrupt sources. Below is a detailed
description of the Configuration Register. The address of this register is Base+5. Table 13
details the bit definitions of the Configuration Register.
Table 13 Configuration Register - Read/Write
TXSRCRXSRCDMTENDMRENINTS0INTS100
D0D1D2D3D4D5D6D7
D7-D6 - Reserved, always 0.
D5-D4 - INTS1, INTS0, INTERRUPT SOURCE AND ENABLE BITS:
These two bits determine the source of the interrupt. The three options are
interrupt on terminal count (INTTC), interrupt from the SCC (INTSCC), and interrupt on Test
Mode (INTTM). When the source is set, that interrupt becomes enabled. Below is the mapping
for these bits.
Table 14 Interrupt Sources
INTTM11
INTSCC01
INTTC10
Interrupts Disabled00
InterruptINTS0INTS1
D3 - DMREN, RECEIVE DMA ENABLE:
When set (logic 1), the signal from the SCC’s receive DMA source is passed on to the
selected ISA bus DRQ. When cleared (logic 0), the SCC cannot drive the receive request signal
onto the ISA bus DRQ.
D2 -DMTEN, TRANSMIT DMA ENABLE:
When set (logic 1), the signal from the SCC’s transmit DMA source is passed on to the
selected ISA bus DRQ. When cleared (logic 0), the SCC cannot drive the transmit request signal
onto the ISA bus DRQ.
MPA-100 User's Manual 8-1