User`s manual

8 SCC General Information

The Serial Communications Controller (SCC) is a dual channel, multi-protocol

data communications peripheral. The MPAC-100 provides a single channel for

communications, however, portions of the second channel can be utilized to support

some special circumstances. The SCC can be configured to satisfy a wide variety of

serial communications applications. Some of its protocol capabilities include:

SDLC/HDLC (Bit Synchronous) Communications

 Abort sequence generation and checking

 Automatic zero insertion and deletion

 Automatic flag insertion between messages

 Address field recognition

 I-field residue handling

 CRC generation and detection

 SDLC loop mode with EOP recognition/loop entry and exit

Byte-oriented Synchronous Communications

 Internal/external character synchronization

 1 or 2 sync characters in separate registers

 Automatic Cyclic Redundancy Check (CRC) generation/detection

Asynchronous Communications

 5, 6, 7, or 8 bits per character

 1, 1-1/2, or 2 stop bits

 Odd, even, or no parity

 Times 1, 16, 32, or 64 x clock modes

 Break generation and detection

 Parity, overrun and framing error detection

NRZ, NRZI, or FM encoding/decoding

Quatech MPAC-100 User's Manual