User`s manual

8.5 SCC Incompatibility Warnings
Due to the SCC implementation used by the MPAC-100, there are two minor
incompatibilities that the software programmer must avoid.
8.5.1 Register Pointer Bits
In a Zilog 85230, the control port register pointer bits can be set in either channel.
With the implementation on the MPAC-100, however, both parts of an SCC control port
access must use the same I/O address.
IMPORTANT
The programmer must be certain not to mix channel
usage during the two-part access of SCC control ports.
It would be highly irregular for code to be written in
The following sequences will work:
Write Control Port A (set pointer bits for desired register)
Read or Write Control Port A (read or write desired channel A register)
Write Control Port B (set pointer bits for desired register)
Read or Write Control Port B (read or write desired channel B register)
The following sequences will NOT work:
Write Control Port A (set pointer bits for desired register)
Read or Write Control Port B (read or write desired channel B register)
Write Control Port B (set pointer bits for desired register)
Read or Write Control Port A (read or write desired channel A register)
8.5.2 Software Interrupt Acknowledge
The 85230's software interrupt acknowledge mechanism is not supported. Bit 5
of Write Register 9 (Software INTACK Enable) is forced to 0. Software must employ the
"Interrupt Without Acknowledge" interrupt method using Read Registers 2 and 3 to
process interrupts.
Quatech MPAC-100 User's Manual
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