User`s manual

9 FIFO Operation

The MPAC-100 is equipped with 1024-byte internal FIFOs in the transmit and

receive data paths. These FIFOs are implemented as extensions of the SCC's small

internal FIFOs. They have been designed to be as transparent as possible to the

software operating the MPAC-100. By using these FIFOs, it is possible to achieve high

data rates despite the MPAC-100 not supporting DMA.

The FIFOs are disabled by default after card insertion, power-up, or a system

reset.

9.1 Enabling and disabling the FIFOs

The FIFOs must be enabled or disabled as a pair. It is not possible to operate

only the transmit FIFO or only the receive FIFO. The FIFOs are enabled by setting bit 2

of the Configuration Register to a logic 1. The FIFOs are disabled by clearing the same

bit.

9.2 Accessing the FIFOs

When the FIFOs are enabled, they are accessed through either the channel A or

channel B SCC Data Port address. Writing to Base+0 or Base+2 will cause a byte to be

written into the transmit FIFO. Reading from Base+0 or Base+2 will cause a byte to be

read from the receive FIFO.

The FIFOs cannot be accessed if they are disabled. If the FIFOs are disabled,

reads or writes of the SCC Data Ports access the receive or transmit register of the

appropriate SCC channel. Any control port writes of SCC write register 8 (transmit

buffer) or control port reads of SCC read register 8 (receive buffer) directly access the

SCC, whether the FIFOs are enabled or not.

9.2.1 Transmit FIFO

The transmit FIFO always services the transmitter of channel A of the SCC. If the

FIFOs are enabled, an I/O write to either SCC Data Port (channel A or channel B) will

write a byte to the transmit FIFO. If the FIFOs are not enabled, an I/O write to the SCC

Data Port will instead write directly to the internal transmit buffer of the specified

channel of the SCC.

Quatech MPAC-100 User's Manual