User`s manual

IMPORTANT

Software can differentiate between the two types of

RX_FIFO interrupts by examining the RXH bit in

the FIFO Status Register. If RXH is clear (logic 0),

the interrupt occurred because of a timeout.

9.4.2 Resetting the FIFOs

The FIFOs are automatically disabled and reset at powerup or when the

MPAC-100 is inserted into a PCI socket. The transmit and receive FIFOs can also be

independently reset by setting and clearing the appropriate bits in the FIFO Control

FIFO's internal read and write pointers. The SCC's internal FIFOs are not affected when

the internal FIFOs are reset.

The internal FIFOs cannot be reset while they are enabled! FIFO reset

commands will be ignored if the internal FIFOs are enabled.

9.4.3 Reading current FIFO status

The FIFO Status Register is a read-only register which always indicates the

current status of both the transmit and receive internal FIFOs. Each FIFO can be

checked for empty, full, and half-full (or more) status at any time. For details, see Table

12 on page 44.

9.4.4 Controlling the FIFOs

The FIFO Control Register is a read-write register which can be used to reset

either or both the receive and transmit internal FIFOs. Receive pattern detection and

receive FIFO timeout modes are also controlled with this register. For details, see

Table 13 on page 45.

9.5 Accessing the SCC while FIFOs are enabled

The SCC channel A and channel B control port registers are always accessible

regardless of whether the internal FIFOs are enabled or disabled. While the FIFOs are

enabled, SCC data port accesses are redirected to the FIFOs. Access to the SCC's

transmit or receive registers while the FIFOs are enabled is possible indirectly by using

the control port and register 8. Any writes of SCC Write Register 8 (transmit buffer) or

reads of SCC Read Register 8 (receive buffer) will bypass the internal FIFOs.

Quatech MPAC-100 User's Manual