User`s manual

9.6 Receive pattern detection

The internal FIFOs are most useful in bit-synchronous operational modes

because the SCC can generate a Special Condition interrupt when the closing flag of a

bit-synchronous frame is received. This allows the SCC to run with per-character

receive interrupts disabled while DMA transfers occur between the SCC and internal

FIFOs.

Byte-synchronous modes such as bisync, however, do not benefit from such a

hardware assist for detecting the end-of-frame condition. On the contrary, with

byte-oriented protocols it is usually necessary to check each byte received against a

table of special function codes (e.g. SYNC, PAD, SDI, STX, EDI, ETX, etc.) to determine

where data and frames begin and end. Unless the frames are of a fixed length, it is

therefore difficult to use DMA with byte-synchronous modes. This would seem to

preclude the use of the MPAC-100's internal FIFOs with byte-oriented protocols.

To make the internal FIFOs more useful in byte-synchronous modes, the

MPAC-100 can watch for a given character to be transferred consecutively a specific

number of times from the SCC into the receive FIFO. When this occurs, the RX_PAT bit

in the Interrupt Status Register (see page 43) is set. For instance, the MPAC-100 can

watch for the end-of-text character to be received, or for three consecutive pad

characters to be received.

For byte-synchronous operation with simple unique markers in the data stream,

this feature may be quite useful. Even if it is not, however, the MPAC-100 can certainly

be operated with per-character interrupts enabled and the internal FIFOs disabled. The

tradeoff will be a heavier interrupt burden and possibly somewhat lower throughput.

NOTE

While most useful in byte-synchronous

modes, the receive pattern detection feature

can be used in any operational mode.

Quatech MPAC-100 User's Manual