User`s manual

11 Configuration Register

The Configuration Register is used to set the interrupt source and enable the

interface between the SCC and the internal FIFOs. The address of this register is

Base+5. Table 10 details the bit definitions of the register.

0RXSRCFIFOEN0INTS0INTS101

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Table 10 --- Configuration Register - Read/Write

Bit 7: Internal Data FIFOs Present --- Reserved, always 1. This

bit can be used as an indicator that internal data FIFOs are present. Other

MPA-series products that are not equipped with internal or external data

FIFOs will return 0 in this bit location.

Bit 6: Reserved, always 0.

Bits 5-4: INTS1, INTS0 --- Interrupt Source and Enable Bits: These

two bits determine the source of the interrupt. The two sources are

interrupt from the SCC (INTSCC), and interrupt on Test Mode (INTTM).

Only one interrupt source can be active at a time. Below is the mapping

for these bits. Note that FIFO-related interrupts will occur only when

INTSCC is chosen.

INTTM

INTSCC

reserved00

Interrupts disabled

Interrupt SourceINTS0INTS1

Bit 3: Reserved, always 0.

Bit 2: FIFOEN --- Internal data FIFO enable: If this

bit is set (logic 1), the internal data FIFOs are enabled. If this bit is clear

(logic 0), the internal data FIFOs are disabled. (See page 31 for full details

on FIFO use.)

Quatech MPAC-100 User's Manual